Control Data Corporation CYBER 180 810 Maintenance And Parts Manual page 90

Register
Options Installed
Environment Control
5-14
6
7
8
9
11
12
16
17
18
19
20
21
0
1
Description
32 MB or 48 MB memory installed
if bit 12=1
8 MB memory installed if bit 12=0
16 MB or 48 MB memory installed
if bit 12=1
8 MB memory installed if bit 12=1
12 MB memory installed
16 MB memory installed
Set for 256K chips
Set when any one of bit 2, 4, and 6
in the configuration switch register
(CSR) is set
Set when either bit 2 or 3 (switch 1)
of CSR is set (32 MB)
Set when either bit 4 or 5 (switch 2)
of CSR is set (16 MB)
Set when either bit 2 or 3 (switch 3)
of CSR is set (8MB)
Set when either bit 4 or 5 (switch 4)
of CSR is set (4MB)
Set when either bit 6 or 7 (switch 5)
of CSR is set (2MB)
Disable parity checking
Disable SECDED
2,5-6,11-15, Not used
20-37
3,4 (Decoded) Write check bits/read check bits/read
Syndrome bits
7
8
9
10
16
17
18
19
38
39
00 -
Perform all memory functions
normally.
01 - Write bits 0,1,4,5,8,9,12, and 13
of the word on the data-in lines
into the check bits of the word
cycled in memory for all writes .
. 10 - Read the check bits of the word
cycled in memory and return these
in bits
0,1-,2,4,5,8,9,12,
and 13
on the data-out lines for all reads.
11 - Read the syndrome bits generated
by the word cycled in memory and
return·these bits on bits
0,1,4,
5,8,9,12, and 13 on the
data-out lines for all reads.
Force even parity
Disable CPU 0 port
Disable IOU port
Disable CPU 1 port
Control pulse width margin
+153
IOU
Control pulse width margin
-153
IOU
Control pulse width margin
+153
CMC
Control pulse width margin
-153
CMC
Force good response code
Disable corrected error log
60469500 B