Control Data Corporation CYBER 180 810 Maintenance And Parts Manual page 71

Memory Configuration Switch (Register)
This 1-byte register is only accessible to the deadstart microprocessor. Its
contents can be changed by the deadstart keyboard's maintenance command SW.
It allows logical reconfiguration of memory to remove failing memory portions
from the address space. The available memory remaining after reconfiguration
is contiguous and starts at address zero as seen from the processor.
The standard central memory using the 64K chip paks allows a maximum memory
configuration of 16 MB, whereas the optional central memory using the 256K
chip paks allows a maximum memory configuration of 64 MB. If memory option of
256K chip paks are installed, bit 12 of the options installed register will be
set.
Depending on the type of memory paks used, the configuration switch register
can represent the positions of either standard configuration switches SW3,
SW4, and SWS, or optional configuration switches SWl, SW2, and SW3 as follow:
Standard memory
Configuration
(64K chip)
Options installed
bit 12
=
0
Optional memory
Configuration
(256K chip)
Options installed
bit 12
=
1
Bits
0,1
2
3
4
5
6
7
0,1
2
3
4
5
6
7
Meaning
Not Used
SW3 Up
SW3 Down
SW4 Up
SW4 Down
sws
Up
sws
Down
Not Used
SWl Up
SWl Down
SW2 Up
SW? Down
SW3 Up
SW3 Down
Action
RMA bit 40 set to
RMA bit 40 set to
RMA bit 41 set to
RMA bit 41 set to
RMA bit 42 set to
RMA bit 42 set to
RMA bit 38 set to
RMA bit 38 set to
RMA bit 39 set to
RMA bit 39 set to
RMA bit 40 set to
RMA bit 40 set to
When pits are zero (center position), normal addressing takes place. When
they are set, memory is degraded according to table 4-10 for 64K chip memory
reconfiguration and table 4-11 for 256K chip memory reconfiguration.
1
0
1
0
1
0
1
0
1
0
1
0
60469500 B
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