Dimm Slots - H3C UniServer R6900 G6 Technology White Paper

Table 10 Processor mezzanine board components
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PCIe5.0 x8 description:

PCIe5.0: Fifth-generation signal rate.

x8: Bus bandwidth.

DIMM slots

As shown in
F1.
Description
MCIO connector C4-P2C (x8 PCIe5.0, for processor 4)
MCIO connector C4-P2A (x8 PCIe5.0, for processor 4)
MCIO connector C4-P1A (x8 PCIe5.0, for processor 4)
MCIO connector C4-P1C (x8 PCIe5.0, for processor 4)
MCIO connector C4-P0C (x8 PCIe5.0, for processor 4)
MCIO connector C4-P0A (x8 PCIe5.0, for processor 4)
MCIO connector C3-P2C (x8 PCIe5.0, for processor 3)
MCIO connector C3-P2A (x8 PCIe5.0, for processor 3)
MCIO connector C3-P1A (x8 PCIe5.0, for processor 3)
MCIO connector C3-P1C (x8 PCIe5.0, for processor 3)
MCIO connector C3-P0C (x8 PCIe5.0, for processor 3)
MCIO connector C3-P0A (x8 PCIe5.0, for processor 3)
MCIO connector C3-P4A (x8 PCIe5.0, for processor 3)
MCIO connector C3-P4C (x8 PCIe5.0, for processor 3)
MCIO connector C3-P3C (x8 PCIe5.0, for processor 3)
MCIO connector C3-P3A (x8 PCIe5.0, for processor 3)
MCIO connector C4-P4A (x8 PCIe5.0, for processor 4)
MCIO connector C4-P4C (x8 PCIe5.0, for processor 4)
MCIO connector C4-P3C (x8 PCIe5.0, for processor 4)
MCIO connector C4-P3A (x8 PCIe5.0, for processor 4)
Figure 10 and Figure 11, DIMM slots are numbered as A0, B0, ..., F0, and A1, B1, ...,
12
Mark
C4-P2C
C4-P2A
C4-P1A
C4-P1C
C4-P0C
C4-P0A
C3-P2C
C3-P2A
C3-P1A
C3-P1C
C3-P0C
C3-P0A
C3-P4A
C3-P4C
C3-P3C
C3-P3A
C4-P4A
C4-P4C
C4-P3C
C4-P3A