H3C UniServer R6900 G6 Technology White Paper page 60

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Table 35 Operating DIMM frequency with different DPC configuration
CPU type
Sapphire Rapids
Installation guidelines
When you install only DDR5 DIMMs, follow these restrictions and guidelines:
Make sure their corresponding processors are present before powering on the server.
As a best practice, install DDR5 DIMMs that have the same product code and DIMM
specification (type, capacity, rank, and frequency). For information about DIMM product codes,
use the component compatibility lookup tool at
http://www.h3c.com/en/home/qr/default.htm?id=66. To install components or replace faulty
DIMMs of other specifications, contact Technical Support.
For the configured memory mode to take effect, make sure the following installation
requirements are met:
Memory mode
Independent
Mirror
NOTE:
In the figures, the black DIMM slots (for example, the F1 slot) are grey colored, and the white
DIMM slots (for example, the F0 slot) are not colored.
Figure 43 DDR5 DIMM population schemes for two processors
Number of DIMMs
H0
2
4
8
12
16
24
32
Figure 44 DDR5 DIMM population schemes for four processors (1)
Number of DIMMs
CH8
H0
4
8
16
24
32
48
64
DDR5
frequency
4800MHz
DIMM population requirements
If two processors are present, see
If four processors are present, see
If two processors are present, this mode is supported only when 16 DIMMs or
32 DIMMs are installed.
If four processors are present, this mode is supported only when 32 DIMMs
or 64 DIMMs are installed.
If four processors are present, see
If four processors are present, see
System board (processor 2)
CH8
CH7
CH6
CH5
H1
G0
G1
F0
F1
E0
E1
A1
System board (processor 2)
CH7
CH6
CH5
H1
G0
G1
F0
F1
E0
E1
A1
DIMM
DPC configuration
1 DPC
2 DPC
DIMM population
CH1
CH2
CH3
CH4
A0
B1
B0
C1
C0
D1
D0
DIMM population
CH1
CH2
CH3
CH4
A0
B1
B0
C1
C0
D1
D0
2
Operating
frequency
4800 MHz
4400 MHz
Figure
43.
Figure 44
and
Figure
Figure
43.
Figure 44
and
Figure
System board (processor 1)
CH8
CH7
CH6
CH5
H0
H1
G0
G1
F0
F1
E0
E1
System board (processor 1)
CH8
CH7
CH6
CH5
H0
H1
G0
G1
F0
F1
E0
E1
DIMM
45.
45.
CH1
CH2
CH3
CH4
A1
A0
B1
B0
C1
C0
D1
D0
CH1
CH2
CH3
CH4
A1
A0
B1
B0
C1
C0
D1
D0

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