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3.18.1 VCO and PLL Self-Calibration
The VCO characteristics vary with temperature and supply voltage changes, as well as the desired
operating frequency. To ensure reliable operation, CC11x1-Q1 includes frequency synthesizer
self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on
power and before using a new frequency (or channel). The number of XOSC cycles for completing the
PLL calibration is given in
The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated
each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is
configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated
when the SCAL command strobe is activated in the IDLE mode.
The calibration values are maintained in SLEEP mode, so the calibration is still valid after
waking up from SLEEP mode (unless supply voltage or temperature has changed
significantly).
To check that the PLL is in lock, the user can program register IOCFGx.GDOx_CFG to 0x0A and use the
lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0,1, or 2). A positive
transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register
FSCAL1. The PLL is in lock if the register content is different from 0x3F (see also the errata notes). For
more robust operation the source code could include a check so that the PLL is re-calibrated until PLL
lock is achieved if the PLL does not lock the first time.
3.19 Voltage Regulators
CC11x1-Q1 contains several on-chip linear voltage regulators, which generate the supply voltage needed
by low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral
parts of the various modules. The user must however make sure that the absolute maximum ratings and
required pin voltages in
core requires one external decoupling capacitor.
Setting the CS pin low turns on the voltage regulator to the digital core and starts the crystal oscillator.
The SO pin on the SPI interface must go low before the first positive edge of SCLK (setup time is given in
Section
2.15).
If the chip is programmed to enter power-down mode, (SPWD strobe issued), the power is turned off after
CS goes high. The power and crystal oscillator are turned on again when CS goes low.
The voltage regulator output should be used only for driving the CC11x1-Q1.
3.20 Output Power Programming
The RF output power level from the device has two levels of programmability, as illustrated in
Firstly, the special PATABLE register can hold up to eight user selected output power settings. Secondly,
the 3-bit FREND0.PA_POWER value selects the PATABLE entry to use. This two-level functionality
provides flexible PA power ramp up and ramp down at the start and end of transmission, as well as ASK
modulation shaping. All the PA power settings in the PATABLE from index 0 up to the
FREND0.PA_POWER value are used.
The power ramping at the start and at the end of a packet can be turned off by setting
FREND0.PA_POWER to zero and then program the desired output power to index 0 in the PATABLE.
If OOK modulation is used, the logic 0 and logic 1 power levels shall be programmed to index 0 and 1
respectively.
Copyright © 2009–2010, Texas Instruments Incorporated
Table
3-14.
Table 3-1
and
Section 2.1
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SWRS076B – 11-07-22-013 - APRIL 2009 – REVISED APRIL 2010
NOTE
are not exceeded. The voltage regulator for the digital
CC11x1-Q1
Figure
3-21.
Detailed Description
53
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