Transit Ion T O S3; Transit Ion T O S4; Transit Ion T O S5; Transit Ion T O Full- On - Intel Core 2 Duo User Manual

Th e or y of Ope r a t ion—I nt e l
3 .6 .1 Tr a nsit ion t o S3
I f enabled, t he t ransit ion t o S3 from t he full- on st at e can be accom plished in t he
following ways:
• The OS perform s t he t ransit ion t hrough soft ware.
• Press t he front panel power but t on for less t han four seconds ( assum ing t he OS
power m anagem ent support has been enabled) .
Not e: The power but t on is accessed by adding a swit ch t o t he pins 5 and 6 on t he front panel
header J8J1.
3 .6 .2 Tr a nsit ion t o S4
" Wake on S4" ( Suspend t o disk) is cont rolled by t he operat ing syst em .
3 .6 .3 Tr a nsit ion t o S5
The t ransit ion t o S5 is accom plished by t he following m eans:
• Press t he front panel power but t on for less t han four seconds ( if enabled t hrough
t he OS) .
• Press t he front panel power but t on for m ore t han four seconds t o act ivat e power
but t on override.
3 .6 .4 Tr a nsit ion t o Fu ll- On
The t ransit ion t o t he Full- On st at e can be from S3 or S5. The t ransit ion from S3 is a low
lat ency t ransit ion t hat is t riggered by one of t he following wake event s:
• Power m anagem ent t im er expirat ion
• Real Tim e Clock ( RTC) t riggered alarm
• Power but t on act ivat ion
• USB device int errupt
• I CH7M pin PME# assert ion
• AC power loss
For AC power loss, t he syst em operat ion is defined by regist er set t ings in t he I nt el
I CH7- M. Upon t he ret urn of power, a BI OS opt ion, set prior t o t he power loss, allows
t he syst em t o eit her go im m ediat ely t o t he S5 st at e, or reboot t o t he Full- On st at e, no
m at t er what t he st at e was before t he power loss. Ext ernal logic for t his funct ionalit y is
not necessary. I f t he BI OS rem ains in t he S5 st at e aft er AC power loss, only t he power
but t on or t he RTC alarm can bring t he syst em out of t he S5 st at e. The st at us of enabled
wake event s will be lost .
3 .7 Pow e r M e a sur e m e n t Su ppor t
Power m easurem ent resist ors are provided on t he plat form t o m easure t he power of
m ost subsyst em s. All power m easurem ent resist ors have a t olerance of 1% . The value
of t hese power m easurem ent resist ors are 2 m Ω by default . Power on a part icular
subsyst em is calculat ed using t he following form ula:
May 2007
Order Num ber: 317443- 001US
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9 4 5 GM E Ex pr e ss Chipse t
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I nt el Core
2
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2 Duo processor wit h t he Mobile I nt el
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945GME Express Chipset
Manual
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