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This delay takes place because the CPU is operating so much faster than
the input/output bus that the CPU must be delayed to allow for the
completion of the I/O.
This item allows you to determine the recovery time allowed for 8 bit I/O.
Choices are from NA, 1 to 8 CPU clocks.
16 Bit I/O Recovery Time
This item allows you to determine the recovery time allowed for 16 bit I/O.
Choices are from NA, 1 to 4 CPU clocks.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be
reserved for ISA cards. This memory must be mapped into the memory
space location 15-16MB.
Item
Enabled
Disabled
Passive Release
When Enabled, CPU to PCI bus accesses is allowed during passive
release. Otherwise, the arbiter only accepts another PCI master access
to local DRAM.
The Choice: Enabled, Disabled.
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
The Choice: Enabled, Disabled.
Description
Memory hole supported.
Memory hole not supported.
4-20
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