Testing The Directional Comparison Logic Function - ABB Relion 670 Series Commissioning Manual

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1MRK 504 165-UEN E
11.11.4.1

Testing the directional comparison logic function

Blocking scheme
1.
Inject the polarizing voltage 3U0 at 5% of
the voltage by 65°.
2.
Inject current (65° lagging the voltage) in one phase at about 110% of the set operating
current, and switch the current off with the switch.
3.
Switch the fault current on and measure the operating time of the communication logic.
Use the TRIP signal from the configured binary output to stop the timer.
4.
Compare the measured time with the set value
5.
Activate the CR binary input.
6.
Check that the CRL output is activated when the CR input is activated.
7.
Switch the fault current on (110% of the set operating current) and wait longer than the
set value
8.
Switch the fault current off.
9.
Reset the CR binary input.
10.
Activate the BLOCK digital input.
11.
Switch the fault current on (110% of the set operating current) and wait for a period
longer than the set value
12.
Switch the fault current and the polarizing voltage off.
13.
Reset the BLOCK digital input.
Permissive scheme
1.
Inject the polarizing voltage 3U0, which is 5% of
lagging the voltage by 65°.
2.
Inject current (65° lagging the voltage) into one phase at about 110% of the set operating
current, and switch the current off with the switch.
3.
Switch the fault current on, (110% of the set operating current) and wait longer than the
set value
4.
Switch the fault current off.
5.
Activate the CR binary input.
6.
Switch the fault current on (110% of the set operating current) and measure the
operating time of the ECPSCH logic.
Use the TRIP signal from the configured binary output to stop the timer.
7.
Compare the measured time with the setting for
8.
Activate the BLOCK digital input.
9.
Switch the fault current on (110% of the set operating current) and wait for a period
longer than the set value
Transformer protection RET670
Commissioning manual
tCoord .
No TRIP signal should appear.
tCoord .
No TRIP signal should appear.
tCoord .
No TRIP signal should appear, and the CS binary output should be
activated.
tCoord .
© Copyright 2017 ABB. All rights reserved
Testing functionality by secondary injection
UBase (EF4PTOC) where the current is lagging
tCoord .
UBase (EF4PTOC) where the current is
tCoord .
Section 11
M13926-7 v2
M13926-9 v6
M13926-42 v8
233

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