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6.1 Configured States
In this PDN, the PMIC devices have the following four configured power states:
•
Standby
•
Active
•
MCU Only
•
Pwr SoC Error
•
DDR Retention
In
Figure
6-1, the configured PDN power states are shown, along with the transition conditions to move between
the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY and LP_STANDBY are
shown. The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the
TPS6594-Q1 data sheet, see
SLVUC99A – JANUARY 2022 – REVISED JANUARY 2022
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Section
8.
Copyright © 2022 Texas Instruments Incorporated
Pre-Configurable Finite State Machine (PFSM) Settings
Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for
31
Jacinto™ 7 J721E, PDN-0C
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