Table of Contents
Advertisement
Quick Links
www.ti.com
User's Guide
TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide
for Jacinto™ 7 J721E, PDN-0B
This user's guide can be used as a guide for integrating the TPS65941212-Q1 and TPS65941111-Q1 power
management integrated circuits (PMICs) into a system powering the Automotive Jacinto™ 7 DRA829 or
TDA4VM processor.
1
Introduction.............................................................................................................................................................................2
2 Device Versions......................................................................................................................................................................
Connections..........................................................................................................................................................4
3.1 Power Mapping..................................................................................................................................................................
Mapping.................................................................................................................................................................7
4.1 Achieving ASIL-B System Requirements.........................................................................................................................
4.2 Achieving up to ASIL-D System Requirements................................................................................................................
Settings..............................................................................................................................................................13
5.2 Device Identification Settings...........................................................................................................................................
5.3 BUCK Settings.................................................................................................................................................................
Settings....................................................................................................................................................................16
5.5 VCCA Settings.................................................................................................................................................................
5.6 GPIO Settings..................................................................................................................................................................
5.7 Finite State Machine (FSM) Settings...............................................................................................................................
Settings..............................................................................................................................................................20
Settings...................................................................................................................................................23
5.10 Miscellaneous Settings..................................................................................................................................................
Settings............................................................................................................................................................25
5.12 Multi-Device Settings.....................................................................................................................................................
5.13 Watchdog Settings.........................................................................................................................................................
6 Pre-Configurable Finite State Machine (PFSM) Settings..................................................................................................
6.1 Configured States............................................................................................................................................................
6.2 PFSM Triggers.................................................................................................................................................................
6.3 Power Sequences............................................................................................................................................................
Changes.......................................................................................................................................................49
8 References............................................................................................................................................................................
9 Revision History...................................................................................................................................................................
Trademarks
Jacinto
™
is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
SLVUC32B - JUNE 2021 - REVISED FEBRUARY 2022
Submit Document Feedback
ABSTRACT
Table of Contents
Systems..............................................................................................................................10
Settings........................................................................................................................13
TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7
Copyright © 2022 Texas Instruments Incorporated
Table of Contents
2
4
11
11
14
14
17
17
20
24
26
26
26
27
28
29
50
50
1
J721E, PDN-0B
Advertisement
Table of Contents
Subscribe to Our Youtube Channel
Related Manuals for Texas Instruments TPS65941212-Q1
Summary of Contents for Texas Instruments TPS65941212-Q1
-
Page 1: Table Of Contents
TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 J721E, PDN-0B ABSTRACT This user’s guide can be used as a guide for integrating the TPS65941212-Q1 and TPS65941111-Q1 power management integrated circuits (PMICs) into a system powering the Automotive Jacinto™ 7 DRA829 or TDA4VM processor. -
Page 2: Introduction
The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 2-1. TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback... - Page 3 GPIO optimizations found in PDN-0C. This document describes PDN-0B. SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
-
Page 4: Processor Connections
BIST_FAIL_INT interrupt is set and the device goes to the safe state and main processor voltages are disabled. TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022... - Page 5 • ** VDD_SD_DV, 3.3 V then software changes to 1.8 V per HS-SD. SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
- Page 6 Optional E_1V8 TPS62813- BUCK VDD_DDR_ VDDS_DDR_BIAS, Required Optional Required VDDS_DDR_IO Mem: VDD2 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
-
Page 7: Control Mapping
ASIL-D, compliant dual voltage SD card operation, and LPDDR4x integration. SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B... - Page 8 PDN FEATURES Base PDN MCU-only TPS62813-Q1 Suspend-to-RAM Figure 3-2. TPS6594-Q1 Digital Connections TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 9 PMICA_GPIO8 WDOG GPIO_9 PMICA_GPIO9 GPIO_10 WKUP1 PMIC_POWER_EN1 Required nRSTOUT_ GPIO_11 H_SOC_PORz_1V8 Required SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
-
Page 10: Supporting Functional Safety Systems
ASIL-D rating. See the DRA829/TDA4VM Safety Manual for Jacinto 7 Processors for a complete list of functional safety system assumptions. TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright ©... -
Page 11: Achieving Asil-B System Requirements
POK monitor built into the VDDSHV0_MCU voltage domain of the processor. The unused feedback pin of BUCK3 on TPS65941212-Q1, FB_B3, is assigned to monitor the VDD_DDR_1V1 voltage supplied by the external BUCK regulator. For monitoring the load switch voltage that supplies the Main I/O, an unused feedback pin of the TPS65941111- Q1 (FB_B3 or FB_B4) can be configured through I2C and connected to the output of the load switch to enable monitoring. - Page 12 TLV73318P-Q1 LDO-A VDD_EFUSE_1V8 None 1. Rail Group settings for the TPS65941212-Q1 and TPS65941111-Q1 are found in Table 5-7. 2. Power rails VDD_DDR_1V1 and VDD1_LPDDR4_1V8 are safety critical but do not required direct voltage or current monitoring since other means are available (for example, SoC internal timeout gaskets and ECC checkers) provide diagnostic coverage to detect faults in the DDR voltage.
-
Page 13: Static Nvm Settings
2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated... -
Page 14: Device Identification Settings
BUCK3_VOUT_1 BUCK3_VOUT_1 BUCK3_PLDN Enabled; Pull-down resistor Enabled; Pull-down resistor BUCK3_RV_SEL Disabled Disabled TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 15 +5% / +50 mV BUCK5_UV_THR -5% / -50 mV -5% / -50 mV SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
-
Page 16: Ldo Settings
5.4 LDO Settings These settings detail the default voltages, configurations, and monitoring of the LDO rails. All these settings can be changed though I C after startup. Note: only TPS65941212-Q1 device contains LDO outputs. Table 5-4. LDO NVM Settings TPS65941212-Q1... -
Page 17: Vcca Settings
GPIO1_DEGLITCH_EN 0x0 No deglitch, only No deglitch, only synchronization. synchronization. SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated... - Page 18 GPIO7_DEGLITCH_EN 0x1 8 us deglitch time. 8 us deglitch time. TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 19 Open-drain output Open-drain output GPIO_OUT_1 GPIO1_OUT GPIO2_OUT GPIO3_OUT GPIO4_OUT GPIO5_OUT GPIO6_OUT GPIO7_OUT GPIO8_OUT SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
-
Page 20: Finite State Machine (Fsm) Settings
Low; Masking sets signal Low; Masking sets signal value to '0' value to '0' TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 21 Interrupt generated LDO3_ILIM_MASK Interrupt generated Interrupt generated LDO4_ILIM_MASK Interrupt generated Interrupt generated SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
- Page 22 Interrupt generated SOC_PWR_ERR_MAS Interrupt generated Interrupt generated ORD_SHUTDOWN_MA Interrupt generated Interrupt generated TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
-
Page 23: Powergood Settings
PGOOD_SEL_LDO1 Masked Masked PGOOD_SEL_LDO2 Masked Masked PGOOD_SEL_LDO3 Masked Masked PGOOD_SEL_LDO4 Masked Masked SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated... -
Page 24: Miscellaneous Settings
Mixed dwell Mixed dwell SS_DEPTH No modulation No modulation SPREAD_SPECTRUM SS_PARAM1 SS_PARAM2 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 25: Interface Settings
I2C1_ID_REG I2C1_ID 0x48 0x48 0x4c 0x4C I2C2_ID_REG I2C2_ID 0x12 0x12 0x13 0x13 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated... -
Page 26: Multi-Device Settings
6 Pre-Configurable Finite State Machine (PFSM) Settings This section describes the default PFSM settings of the TPS6594-Q1 devices. These settings cannot be changed after device startup. TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright ©... -
Page 27: Configured States
After these instructions are executed the PMICs wait for a valid ON Request (SU_ACTIVE trigger) before entering the ACTIVE state. The definition for each power state is described below: SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B... -
Page 28: Pfsm Triggers
No State TPS65941111-Q1 Edge Change LDO1 output is 3.3 V in BYPASS mode TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 29: Power Sequences
The TO_SAFE_SEVERE and TO_SAFE are distinct sequences which occur when transition to the SAFE state. Both sequences shut down all rails without delay. The TO_SAFE_SEVERE sequence immediately ceases SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B... - Page 30 TO_SAFE sequence does not reset the BUCK regulators until after the regulators are turned off as shown in Figure 6-2. TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback...
- Page 31 GPIO11 TPS65941111-Q1 0 us EN_3V3IO_LDSW Figure 6-2. TO_SAFE_SEVERE and TO_SAFE Power Sequence SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
- Page 32 Both the TO_SAFE_ORDERLY and TO_STANDBY sequences set the SPMI_LP_EN and FORCE_EN_DRV_LOW in the TPS65941212 while only the SPMI_LP_EN is set in the TPS65941111. TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022...
- Page 33 GPIO11 TPS65941111-Q1 3500 us EN_3V3IO_LDSW Figure 6-3. TO_SAFE_ORDERLY and TO_STANDBY Power Sequence SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
- Page 34 MCU_POWER_ERR, however, in order to maintain consistency all of the regulators are returned to the values stored in NVM and the recovery counter is incremented. TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022...
- Page 35 2000 us MCU_PORZ nRSTOUT_SOC TPS65941212-Q1 2000 us PORZ Figure 6-4. ACTIVE_TO_WARM Power Sequence SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
- Page 36 // Set AMUXOUT_EN and CLKMON_EN, clear LPM_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE3 // Clear SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback...
- Page 37 VDDSHV5 LDO2 TPS65941111-Q1 3500 us VDDA_3P3_USB Figure 6-6. PWR_SOC_ERROR with I2C_7 High SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
- Page 38 The MCU relevant BUCK and LDOs are reset to their default voltages at the time indicated in Figure 6-8, and finally the MCU_PORz signal is set high. TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback...
- Page 39 MCU rails, in the event that they are not already active (when transitioning from STANDBY to MCU_ONLY for example). There are two cases for this sequence, based off the value stored in the I2C_7 register bit of primary TPS65941212-Q1. If the bit is low, then VDD1, EN_DDR_BUCK and mVDDS_DDR_x, are disabled;...
- Page 40 // Clear LPM_EN REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE3 // Clear SPMI_LP_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 41 MCU_PORZ Figure 6-9. TO_MCU with I2C_7 HIGH; VDD1 is Unchanged in Sequence SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
- Page 42 MCU_PORZ MCU_PORZ MCU_PORZ Figure 6-10. TO_MCU with I2C_7 LOW, VDD1 is Disabled in Sequence TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 43 BUCK3 as described in Table 5-3. SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
- Page 44 12700 us MCU_PORZ nRSTOUT_SOC TPS65941212-Q1 12700 us PORZ Figure 6-11. TO_ACTIVE Sequence TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 45 REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x18 MASK=0xE7 //TPS65941111 // Set SPMI_LP_EN REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
- Page 46 EN_MCU3V3IO_LDSW EN_MCU3V3IO_LDSW EN_MCU3V3IO_LDSW Figure 6-12. TO_S2R and I2C_7 is Low on Both PMICs TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 47 EN_MCU3V3IO_LDSW Figure 6-13. To S2R and I2C_7 is High in Both PMICs SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated...
- Page 48 The TPS65941212 device also performs an additional 16 ms delay based upon the contents of the register (PFSM_DELAY_REG_2) to ensure that the TPS65941212 sequence finishes last. TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022...
-
Page 49: Impact Of Nvm Changes
In the event of a readback error on the nINT pin, a unmasked. Table 5-8 MODERATE_ERR_INT occurs resulting in the transition to SAFE_RECOVERY. SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 Submit Document Feedback J721E, PDN-0B Copyright © 2022 Texas Instruments Incorporated... -
Page 50: References
Added note to State Transition Triggers for I2C_2....................28 • Added Section 7 .............................. • Added reference to PDN-0C..........................50 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7 SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022 J721E, PDN-0B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 51 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated...
Need help?
Do you have a question about the TPS65941212-Q1 and is the answer not in the manual?
Questions and answers