Pfsm Triggers - Texas Instruments TPS65941213-Q1 User Manual

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clear the VCCA OV and UV masks which are set in the static configurations,
are executed the PMICs wait for a valid ON Request before entering the ACTIVE state. The definition for each
power state is described below:
STANDBY The PMICs are powered by a valid supply on the system power rail (VCCA > VCCA_UV). All
device resources are powered down in the STANDBY state. EN_DRV is forced low in this state.
The processor is in the Off state, no voltage domains are energized. Refer to the
sequence description.
The STANDBY state is also entered when an error occurs and the PMIC transitions out of the
PFSM mission states and into the FSM states. When the device returns from the FSM state
the to PFSM the first state is represented by STANDBY with all of the resources powered down
and EN_DRV forced low. The sequence
PFSM and enters the FSM state SAFE_RECOVERY.
ACTIVE The PMICs are powered by a valid supply. The PMICs are fully functional and supply power
to all PDN loads. The processor has completed a recommended power up sequence with all
voltage domains energized in both MCU and Main processor sections. Refer to the
6.3.8 sequence description.
MCU_ONLY The PMICs are powered by a valid supply. Only the power resources assigned to the MCU
Safety Island are on. Refer to the
Pwr SoC The PMICs are powered by a valid supply. Only the power resources assigned to the MCU
Error Safety Island are on. Refer to the
'B', requiring the PMICs to return to the MCU_ONLY mode. The return to MCU_ONLY mode
and eventually ACTIVE mode is only recommended after the interrupts which caused the
SOC_PWR_ERROR have been cleared.
Retention The PMICs are powered by a valid supply. When the PMICs I2C_7 triggers are set (DDR
Retention), only 3 SoC voltage domains (vdds_ddr_bias, vdds_ddr, and vdds_ddr_c) remain
energized while all other domains are off to minimize total system power. EN_DRV is forced low
in this state. Refer to the

6.2 PFSM Triggers

As shown in Figure 6-1, there are various triggers that can enable a state transition between configured states.
Table 6-1 describes each trigger and its associated state transition from highest priority (Immediate Shutdown)
to lowest priority (I2C_3). Active triggers of higher priority block triggers of lower priority and the associated
sequence.
Trigger Priority (ID)
Immediate
0
(9)
Shutdown
MCU Power Error 1
Orderly
2
(9)
Shutdown
(11)
OFF Request 4
WDOG Error 5
ESM MCU Error 6
ESM SOC Error 7
WDOG Error 8
ESM MCU Error 9
SLVUC99A – JANUARY 2022 – REVISED JANUARY 2022
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Section 6.3.7
Section 6.3.5
Section 6.3.9 sequence description.
Table 6-1. State Transition Triggers
Immediate
REENTERANT
(IMM)
True False
True False
True False
False False
False True
False True
False True
False True
False True
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Pre-Configurable Finite State Machine (PFSM) Settings
Table
Section 6.3.1 is performed before the PMIC leaves the
sequence description.
sequence description. The only active trigger is
PFSM Current State Destination
STANDBY, ACTIVE,
MCU ONLY, Suspend-
to-RAM
STANDBY, ACTIVE,
MCU ONLY, Suspend-
to-RAM
STANDBY, ACTIVE,
MCU ONLY, Suspend-
to-RAM
STANDBY, ACTIVE,
MCU ONLY, Suspend- STANDBY
to-RAM
ACTIVE
ACTIVE
ACTIVE
MCU ONLY MCU ONLY
MCU ONLY MCU ONLY
Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for
5-8. After these instructions
Section 6.3.2
Section
PFSM
Power Sequence or
Function Executed
State
(1)
SAFE TO_SAFE_SEVERE
(1)
SAFE TO_SAFE
(1)
SAFE TO_SAFE_ORDERLY
(2)
TO_STANDBY
ACTIVE
ACTIVE_TO_WARM
ACTIVE
ACTIVE ESM_SOC_ERROR
MCU_TO_WARM
Jacinto™ 7 J721E, PDN-0C
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