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User's Guide
User Guide for Powering Jacinto
Single TPS6594-Q1 PMIC, PDN-2A
This User's Guide can be used as a guide for integrating the TPS65941515-Q1 power management integrated
circuit (PMIC) into a system powering the Automotive Jacinto™ 7 DRA821 processor.
1
Introduction.............................................................................................................................................................................2
2 Device Versions......................................................................................................................................................................
Connections..........................................................................................................................................................3
3.1 Power Mapping..................................................................................................................................................................
Mapping.................................................................................................................................................................6
5 Static NVM Settings..............................................................................................................................................................
5.2 Device Identification Settings...........................................................................................................................................
5.3 BUCK Settings.................................................................................................................................................................
Settings....................................................................................................................................................................15
5.5 VCCA Settings.................................................................................................................................................................
5.6 GPIO Settings..................................................................................................................................................................
5.7 Finite State Machine (FSM) Settings...............................................................................................................................
Settings..............................................................................................................................................................19
Settings...................................................................................................................................................21
5.10 Miscellaneous Settings..................................................................................................................................................
Settings............................................................................................................................................................23
5.12 Watchdog Settings.........................................................................................................................................................
6 Pre-Configurable Finite State Machine (PFSM) Settings..................................................................................................
6.1 Configured States............................................................................................................................................................
6.2 PFSM Triggers.................................................................................................................................................................
6.3 Power Sequences............................................................................................................................................................
7 Application Examples..........................................................................................................................................................
Standby...........................................................................................................................................36
7.3 Entering and Existing LP_STANDBY...............................................................................................................................
7.4 GPIO8 and Watchdog......................................................................................................................................................
8 References............................................................................................................................................................................
Trademarks
™
Jacinto
is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
SLVUCD4 - NOVEMBER 2022
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ABSTRACT
Table of Contents
Systems................................................................................................................................9
Requirements.........................................................................................................................10
Requirements................................................................................................................10
Settings........................................................................................................................12
RETENTION........................................................................................................35
User Guide for Powering Jacinto
Copyright © 2022 Texas Instruments Incorporated
TM
7 J7200 DRA821 with
TM
7 J7200 DRA821 with Single TPS6594-Q1
Table of Contents
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PMIC, PDN-2A
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Related Manuals for Texas Instruments TPS65941515-Q1
Summary of Contents for Texas Instruments TPS65941515-Q1
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Page 1: Table Of Contents
7 J7200 DRA821 with Single TPS6594-Q1 PMIC, PDN-2A ABSTRACT This User’s Guide can be used as a guide for integrating the TPS65941515-Q1 power management integrated circuit (PMIC) into a system powering the Automotive Jacinto™ 7 DRA821 processor. Table of Contents Introduction.....................................2... -
Page 2: Introduction
TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 3: Processor Connections
Processor Connections 3 Processor Connections This section details how the TPS65941515-Q1 power resources and GPIO signals are connected to the processor and other peripheral components. 3.1 Power Mapping Figure 3-1 shows the power mapping between the TPS65941515-Q1 PMIC and peripheral regulators to power the processor and associated accessories. - Page 4 * VDD_CPU_AVS, boot voltage of 0.8 V then software sets device specific AVS • ** VPP_EFUSE_1V8, is optional User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 5 Mem: LPDDR4_VDD1 DR4_1V8 TLV73318P LDO-C VPP_EFUS VPP_x(EFUSE) E_1V8 'R' is required and 'O' is optional. SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated...
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Page 6: Control Mapping
GPIO and DDR Retention modes, functional safety up to ASIL-D, and compliant dual voltage SD card operation. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 7 Base PDN Retention Figure 3-2. TPS65941515-Q1 Digital Connections 1. PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. Please refer to the SLVUCD4 –...
- Page 8 LP_WKUP1 function is masked in the static settings. Instructions for unmasking the function are provided in RETENTION, Entering and Exiting Standby and Entering and Existing LP_STANDBY. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 9: Supporting Functional Safety Systems
4 Supporting Functional Safety Systems By using the TPS65941515-Q1 solution to power the DRA821 processor, the system can leverage the following PMIC functional safety features: •... -
Page 10: Achieving Asil-B System Requirements
C using the ESM_SOC_EN register bit. For the TPS65941515, an SoC reset is not supported but an interrupt fires and the nINT pin driven low. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 11: Static Nvm Settings
None TLV73318P-Q1 LDO-C VPP_EFUSE_1V8 None 1. Rail Group settings for the TPS65941515-Q1 are found in Table 5-7. 2. Power rails VDD_DDR_1V1 and VDD1_LPDDR4_1V8 are safety critical but do not required direct voltage or current monitoring since other means are available (for example, SoC internal timeout gaskets and ECC checkers) provide diagnostic coverage to detect faults in the DDR voltage. -
Page 12: Application-Based Configuration Settings
220 nH BUCK5 4.4 MHz VOUT Less than 1.9 V Single Phase 220 nH User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 13: Device Identification Settings
BUCK3_VOUT_1 BUCK3_PLDN Enabled; Pull-down resistor BUCK3_RV_SEL Enabled BUCK3_CONF BUCK3_SLEW_RATE 5.0 mV/μs BUCK3_ILIM 5.5 A SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated... - Page 14 -5% / -50 mV BUCK5_PG_WINDOW BUCK5_OV_THR +5% / +50 mV BUCK5_UV_THR -5% / -50 mV User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 15: Ldo Settings
-5% / -50 mV LDO4_PG_WINDOW LDO4_OV_THR +5% / +50 mV LDO4_UV_THR -5% / -50 mV SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated... -
Page 16: Vcca Settings
LP_WKUP1 GPIO4_PU_SEL Pull-down resistor selected GPIO4_PU_PD_EN Enabled; Pull-up/pull-down resistor. GPIO4_DEGLITCH_EN 8 us deglitch time. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 17 GPIO11 GPIO11_PU_SEL Pull-down resistor selected GPIO11_PU_PD_EN Disabled; Pull-up/pull-down resistor. GPIO11_DEGLITCH_EN No deglitch, only synchronization. SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated...
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Page 18: Finite State Machine (Fsm) Settings
SOC power error Not used in this NVM configuration. SEVERE_ERR_TRIG Immediate shutdown FSM_TRIG_SEL_2 MODERATE_ERR_TRIG Orderly shutdown User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 19: Interrupt Settings
Interrupt generated BUCK4_ILIM_MASK Interrupt generated MASK_BUCK5 BUCK5_ILIM_MASK Interrupt generated BUCK5_OV_MASK Interrupt generated BUCK5_UV_MASK Interrupt generated SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated... - Page 20 SOFT_REBOOT_MASK Interrupt generated MASK_MISC TWARN_MASK Interrupt generated BIST_PASS_MASK Interrupt generated EXT_CLK_MASK Interrupt not generated. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 21: Powergood Settings
PGOOD_SEL_BUCK4 Masked PGOOD_SEL_2 PGOOD_SEL_BUCK5 Masked PGOOD_SEL_3 PGOOD_SEL_LDO1 Masked PGOOD_SEL_LDO2 Masked PGOOD_SEL_LDO3 Masked PGOOD_SEL_LDO4 Masked SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated... -
Page 22: Miscellaneous Settings
LDO3_RV_TIMEOUT 16ms LDO4_RV_TIMEOUT 16ms USER_SPARE_REGS USER_SPARE_1 USER_SPARE_2 USER_SPARE_3 USER_SPARE_4 ESM_MCU_MODE_ CFG ESM_MCU_EN ESM_MCU disabled. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 23: Interface Settings
Register Name Field Name Value Description WD_LONGWIN_CFG WD_LONGWIN 0xff 0xff WD_THR_CFG WD_EN Watchdog enabled. SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated... -
Page 24: Pre-Configurable Finite State Machine (Pfsm) Settings
This section describes the default PFSM settings of the TPS6594-Q1 devices. These settings cannot be changed after device startup. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 25: Configured States
The hardware states are part of the fixed device power Finite State Machine (FSM) and described in the TPS6594-Q1 data sheet, see Section SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated... - Page 26 Off state, no voltage domains are energized. Refer to the Section 6.3.2 sequence description. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 27: Pfsm Triggers
No State No Sequence low and ACTIVE, Suspend-to- False False NSLEEP2 goes Change Executed high SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated... -
Page 28: Power Sequences
BUCK regulators until after the regulators are turned off. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... - Page 29 (LP_STANDBY_SEL=1) states, rather than going to the SAFE state. The power sequence for both of these events is shown in Figure 6-3. SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated...
- Page 30 LP_STANDBY_SEL is false, then the PMIC remains in the mission state defined by STANDBY in Configured States. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 31 TPS65941515-Q1 0 us VDD_DDR_1V1 nRSTOUT TPS65941515-Q1 2000 us H_SOC_PORz_1V8 Figure 6-4. ACTIVE_TO_WARM Power Sequence SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated...
- Page 32 GPIOs that are not supplying the retention rails, as described in Figure User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
- Page 33 GPIO11 TPS65941515-Q1 2000 us EN_SOC_VIO Figure 6-6. TO_RETENTION when I2C_6 and I2C_7 are Low SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated...
- Page 34 At the end of the sequence, PMIC sets the LPM_EN and clears the CLKMON_EN and AMUXOUT_EN bits. User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
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Page 35: Application Examples
After the RTC Timer interrupt has occurred and the PMIC returns to the ACTIVE state SLVUCD4 – NOVEMBER 2022 User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 Submit Document Feedback PMIC, PDN-2A Copyright © 2022 Texas Instruments Incorporated... -
Page 36: Entering And Exiting Standby
WD_PWR_HOLD must be cleared. Write 0x12:0x09:0x00:0xFB // Clear WD_PWRHOLD Write 0x12:0x09:0x40:0xBF // Enable Watchdog User Guide for Powering Jacinto 7 J7200 DRA821 with Single TPS6594-Q1 SLVUCD4 – NOVEMBER 2022 PMIC, PDN-2A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 37: References
Texas Instruments, TPS6594-Q1 Power Management IC (PMIC) with 5 Bucks and 4 LDOs for Safety- Relevant Automotive Applications data sheet • Texas Instruments, TPS6594-Q1 Safety Manual (request through mySecure) • Texas Instruments, TPS6594-Q1 Schematic PCB Checklist application note SLVUCD4 – NOVEMBER 2022... - Page 38 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated...