Silicon Laboratories Giant Gecko EFM32GG Reference Manual

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...the world's most energy friendly microcontrollers

EFM32GG Reference Manual

Giant Gecko Series

• 32-bit ARM Cortex-M3 processor running at up to 48 MHz

• Up to 1024 kB Flash and 128 kB RAM memory

• Energy efficient and autonomous peripherals

• Ultra low power Energy Modes with sub-µA operation

• Fast wake-up time of only 2 µs

The EFM32GG microcontroller series revolutionizes the 8- to 32-bit market with a

combination of unmatched performance and ultra low power consumption in both

active- and sleep modes. EFM32GG devices consume as little as 219 µA/MHz in run

mode.

EFM32GG's low energy consumption outperforms any other available 8-, 16-,

and 32-bit solution. The EFM32GG includes autonomous and energy efficient

peripherals, high overall chip- and analog integration, and the performance of the

industry standard 32-bit ARM Cortex-M3 processor.

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Summary of Contents for Silicon Laboratories Giant Gecko EFM32GG

Page 1 ...the world's most energy friendly microcontrollers EFM32GG Reference Manual Giant Gecko Series • 32-bit ARM Cortex-M3 processor running at up to 48 MHz • Up to 1024 kB Flash and 128 kB RAM memory • Energy efficient and autonomous peripherals •...
Page 2: Energy Friendly Microcontrollers
...the world's most energy friendly microcontrollers 1 Energy Friendly Microcontrollers 1.1 Typical Applications The EFM32GG microcontroller is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications. These devices are developed to minimize the energy consumption by lowering both the power and the active time, over all phases of MCU operation.
Page 3: About This Document
...the world's most energy friendly microcontrollers 2 About This Document This document contains reference material for the EFM32GG series of microcontrollers. All modules and peripherals in the EFM32GG series devices are described in general terms. Not all modules are present in all devices, and the feature set for each device might vary. Such differences, including pin- out, are covered in the device-specific datasheets.
Page 4: Related Documentation
...the world's most energy friendly microcontrollers Reserved Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the Register Description. Reserved bits might be read as 1 in future devices. Reset Value The reset value denotes the value after reset.
Page 5: System Overview
...the world's most energy friendly microcontrollers 3 System Overview 3.1 Introduction The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32GG microcontroller is well suited for any battery operated application, as well as other systems requiring high performance and low-energy consumption, see Figure 3.1 (p.
Page 6: Features
...the world's most energy friendly microcontrollers Note In the energy mode indicator, the numbers indicates Energy Mode, i.e EM0-EM4. 3.3 Features 3.3.1 MCU Features • ARM Cortex-M3 CPU platform • High Performance 32-bit processor @ up to 48 MHz • Memory Protection Unit •...
Page 7: Energy Modes
...the world's most energy friendly microcontrollers • Timers/Counters • 4× 16-bit Timer/Counter • 3 Compare/Capture/PWM channels • Dead-Time Insertion on TIMER0 • 16-bit Low Energy Timer • 1× 24-bit and 1× 32-bit Real-Time Counter • 3× 8/16-bit Pulse Counter • Asynchronous pulse counting/quadrature decoding •...
Page 8: Product Overview
...the world's most energy friendly microcontrollers wake-up time, makes it attractive to remain in low energy modes for long periods and thus saving energy consumption. Throughout this document, the first figure in every module description contains an Energy Mode Indicator showing which energy mode(s) the module can operate (see Table 3.1 (p. 8) ). Table 3.1.
Page 9 ...the world's most energy friendly microcontrollers 230F1024 1024 128 QFN64 (12) (16) 232F512 TQFP64 (11) (16) 232F1024 1024 128 TQFP64 (11) (16) 280F512 LQFP100 (12) (16) 280F1024 1024 128 LQFP100 (12) (16) 290F512 LFBGA112 (12) (16) 290F1024 1024 128 LFBGA112 (12) (16) 295F512...
Page 10: Device Revision
...the world's most energy friendly microcontrollers 890F1024 1024 128 8x36 3+2 LFBGA112 (12) (16) 895F512 8x36 3+2 VFBGA120 (12) (16) 895F1024 1024 128 8x36 3+2 VFBGA120 (12) (16) 900F512 8x36 3+2 Wafer (12) (16) 900F1024 1024 128 8x36 3+2 Wafer (12) (16) 940F512...
Page 11 ...the world's most energy friendly microcontrollers For the latest revision of the Giant Gecko family, the chip family number is 0x02 and the major revision number is 0x01. The minor revision number is to be interpreted according to Table 3.3 (p. 11) . Table 3.3.
Page 12: System Processor
...the world's most energy friendly microcontrollers 4 System Processor Quick Facts What? 0 1 2 3 The industry leading Cortex-M3 processor from ARM is the CPU in the EFM32GG microcontrollers. Why? CM3 Core The ARM Cortex-M3 is designed for exceptional short response time, high 3 2 - bit ALU code density, and high 32-bit throughput Single cycle...
Page 13: Functional Description
...the world's most energy friendly microcontrollers • Unaligned data storage and access • Continuous storage of data requiring different byte lengths • Data access in a single core clock cycle • Integrated power modes • Sleep Now mode for immediate transfer to low power state •...
Page 14: Lcd
...the world's most energy friendly microcontrollers IRQ # Source I2C1 GPIO_ODD TIMER1 TIMER2 TIMER3 USART1_RX USART1_TX LESENSE USART2_RX USART2_TX UART0_RX UART0_TX UART1_RX UART1_TX LEUART0 LEUART1 LETIMER0 PCNT0 PCNT1 PCNT2 BURTC VCMP www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 15: Memory And Bus System
...the world's most energy friendly microcontrollers 5 Memory and Bus System Quick Facts What? A low latency memory system, including low energy flash and RAM with data retention, 0 1 2 3 makes extended use of low-power energy- modes possible. Why? RAM retention reduces the need for storing data in flash and enables frequent use of the...
Page 16: Functional Description
...the world's most energy friendly microcontrollers Figure 5.1. EFM32GG Bus System Flash Cortex AHB Multilayer ICode Bus Matrix DCode System Peripheral 0 AHB/ APB Bridge USB DMA Peripheral n 5.2 Functional Description The memory segments are mapped together with the internal segments of the Cortex-M3 into the system memory map shown by Figure 5.2 (p.
Page 17: Memory Sram Area Set/Clear Bit
...the world's most energy friendly microcontrollers Figure 5.2. System Address Space The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32GG. When running code located in SRAM starting at this address, the Cortex-M3 uses the System bus to fetch instructions.
Page 18: Memory System Core Peripherals
...the world's most energy friendly microcontrollers where address is the address of the 32-bit word containing the bit to modify, and bit is the index of the bit in the 32-bit word. To modify a bit in the Peripheral area, use the following address: Memory Peripheral Area Bit Modification bit_address = 0x42000000 + (address –...
Page 19 ...the world's most energy friendly microcontrollers Table 5.3. Memory System Peripherals Peripherals Address Range Module Name 0x400CC000 - 0x400CC3FF 0x40010C00 - 0x40010FFF TIMER3 0x40010800 - 0x40010BFF TIMER2 0x40010400 - 0x400107FF TIMER1 0x40010000 - 0x400103FF TIMER0 0x4000E400 - 0x4000E7FF UART1 0x4000E000 - 0x4000E3FF UART0 0x4000C800 - 0x4000CBFF USART2...
Page 20: Access To Low Energy Peripherals (Asynchronous Registers)
...the world's most energy friendly microcontrollers The Cortex-M3, the DMA Controller, and the peripherals run on clocks that can be prescaled separately. When accessing a peripheral which runs on a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition to master arbitration, is given by: Memory Wait Cycles with Clock Equal or Faster than HFCORECLK = 2 + N (5.3)
Page 21: Write Operation To Low Energy Peripherals
...the world's most energy friendly microcontrollers 5.3.1.1.1 Delayed synchronization After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corresponding busy flag in the <module_name>_SYNCBUSY register (e.g. LEUART_SYNCBUSY) is set. This flag is set as long as synchronization is in progress and is cleared upon completion.
Page 22: Flash
...the world's most energy friendly microcontrollers 5.3.1.2 Reading When reading from Low Energy Peripherals, the data is synchronized regardless of the originating clock domain. Registers updated/maintained by the Low Energy Peripheral are read directly from the Low Energy clock domain. Registers residing in the core clock domain, are read from the core clock domain. See Figure 5.4 (p.
Page 23: Sram
...the world's most energy friendly microcontrollers • Minimum 20 000 erase cycles • More than 10 years data retention at 85°C • Lock-bits for memory protection • Data retention in any state 5.5 SRAM The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute instructions from SRAM, and the DMA may used to transfer data between the SRAM, Flash and peripherals.
Page 24 ...the world's most energy friendly microcontrollers DI Address Register Description 0x0FE081B8 ADC0_CAL_VDD [14:8]: Gain for VDD reference, [6:0]: Offset for VDD reference. 0x0FE081BA ADC0_CAL_5VDIFF [14:8]: Gain for 5VDIFF reference, [6:0]: Offset for 5VDIFF reference. 0x0FE081BC ADC0_CAL_2XVDD [14:8]: Reserved (gain for this reference cannot be calibrated), [6:0]: Offset for 2XVDD reference.
Page 25: Dbg - Debug Interface
...the world's most energy friendly microcontrollers 6 DBG - Debug Interface Quick Facts What? 0 1 2 3 The DBG (Debug Interface) is used to program and debug EFM32GG devices. Why? The Debug Interface makes it easy to re- program and update the system in the field, and allows debugging with minimal I/O pin usage.
Page 26: Debug Lock And Device Erase
...the world's most energy friendly microcontrollers • Serial Wire Clock input (SWCLK): This pin is enabled after reset and has a built-in pull down. • Serial Wire Data Input/Output (SWDIO): This pin is enabled after reset and has a built-in pull-up. •...
Page 27: Device Unlock
...the world's most energy friendly microcontrollers The debugger can access the AAP-registers, and only these registers just after reset, for the time of the AAP-window outlined in Figure 6.2 (p. 27) . If the device is locked, access to the core and bus-system is blocked even after code execution starts, and the debugger can only access the AAP-registers.
Page 28: Register Map
...the world's most energy friendly microcontrollers 6.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 AAP_CMD Command Register 0x004 AAP_CMDKEY Command Key Register 0x008 AAP_STATUS Status Register 0x0FC AAP_IDR AAP Identification Register 6.6 Register Description 6.6.1 AAP_CMD - Command Register Offset...
Page 29 ...the world's most energy friendly microcontrollers Name Reset Access Description The key value must be written to this register to write enable the AAP_CMD register. After AAP_CMD is written, this register should be cleared to excecute the command. Value Mode Description 0xCFACC118 WRITEEN...
Page 30: Msc - Memory System Controller
...the world's most energy friendly microcontrollers 7 MSC - Memory System Controller Quick Facts What? The user can perform Flash memory read, read configuration and write operations through the Memory System Controller (MSC) . Why? The MSC allows the application code, user data and flash lock bits to be stored in non- volatile Flash memory.
Page 31: Features
...the world's most energy friendly microcontrollers divided into two blocks; the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data.
Page 32: Lock Bits
...the world's most energy friendly microcontrollers Table 7.1. MSC Flash Memory Mapping Block Page Base address Write/Erase by Software Purpose/Name Size readable Main 0x00000000 Software, debug Yes User code and data 512 kB - 1024 Software, debug Yes 0x000FF000 Software, debug Yes Reserved 0x00100000 Reserved for flash...
Page 33 ...the world's most energy friendly microcontrollers Word 127 is the debug lock word (DLW). The four LSBs of this word are the debug lock bits. If these bits are 0xF, then debug access is enabled. If the bits are not 0xF, then debug access to the core is locked. See Section 6.4 (p.
Page 34 ...the world's most energy friendly microcontrollers 7.3.4.4 Suppressed Conditional Branch Target Prefetch (SCBTP) MSC offers a special instruction fetch mode which optimizes energy consumption by cancelling Cortex- M3 conditional branch target prefetches. Normally, the Cortex-M3 core prefetches both the next sequential instruction and the instruction at the branch target address when a conditional branch instruction reaches the pipeline decode stage.
Page 35 ...the world's most energy friendly microcontrollers Figure 7.1. Instruction Cache Instruction Cache Cache Look- up Logic ICODE ICODE Access AHB- Lite Bus AHB- Lite Bus Filter 128x 32 SRAM IDCODE Cortex AHB- Lite Bus IDCODE CODE Perform ance Counters Mem ory Space DCODE AHB- Lite Bus By default, the instruction cache is automatically invalidated when the contents of the flash is changed...
Page 36 ...the world's most energy friendly microcontrollers 7.3.4.7 Instruction Prefetch The MSC also includes instruction prefetch capability for the internal flash memory. This feature is by default disabled, but can be enabled by setting PREFETCH in MSC_READCTRL. The prefetcher works by the assumption that the next instruction word will be needed in the next fetch. This next word is fetched before the word is actually needed.
Page 37 ...the world's most energy friendly microcontrollers Note The MSC_WDATA and MSC_ADDRB registers are not retained when entering EM2 or lower energy modes. 7.3.5.1 Double-Word Writes EFM32GG devices have the ability to do double writes to the flash. This is enabled by setting WDOUBLE in MSC_WRITECTRL, and only has effect on the main pages of the flash.
Page 38: Register Map
...the world's most energy friendly microcontrollers 7.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MSC_CTRL Memory System Control Register 0x004 MSC_READCTRL Read Control Register 0x008 MSC_WRITECTRL Write Control Register 0x00C MSC_WRITECMD Write Command Register...
Page 39 ...the world's most energy friendly microcontrollers 7.5.2 MSC_READCTRL - Read Control Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 17:16 BUSSTRATEGY Strategy for bus matrix...
Page 40 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description Two wait-states inserted for each fetch or read transfer. This mode is required for a core frequency above 32 MHz. WS2SCBTP Two wait-state access with SCBTP enabled. 7.5.3 MSC_WRITECTRL - Write Control Register Offset Bit Position...
Page 41 ...the world's most energy friendly microcontrollers Name Reset Access Description CLEARWDATA Clear WDATA state Will set WDATAREADY and DMA request. Should only be used when no write is active. 11:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ERASEMAIN1 Mass erase region 1 Initiate mass erase of region 1.
Page 42 ...the world's most energy friendly microcontrollers 7.5.6 MSC_WDATA - Write Data Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:0 WDATA 0x00000000 Write Data The data to be written to the address in MSC_ADDR. This register must be written when the WDATAREADY bit of MSC_STATUS is set.
Page 43 ...the world's most energy friendly microcontrollers Name Reset Access Description When set, the last erase or write is aborted due to erase/write access constraints. BUSY Erase/Write Busy When set, an erase or write operation is in progress and new commands are ignored. 7.5.8 MSC_IF - Interrupt Flag Register Offset Bit Position...
Page 44 ...the world's most energy friendly microcontrollers Name Reset Access Description ERASE Erase Done Interrupt Set Set the erase done bit and generate interrupt. 7.5.10 MSC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:4 Reserved...
Page 45 ...the world's most energy friendly microcontrollers Name Reset Access Description Enable the erase done interrupt. 7.5.12 MSC_LOCK - Configuration Lock Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 LOCKKEY 0x0000...
Page 46 ...the world's most energy friendly microcontrollers 7.5.14 MSC_CACHEHITS - Cache Hits Performance Counter Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19:0 CACHEHITS 0x00000...
Page 47 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PERIOD Sets the timebase period Decides whether TIMEBASE specifies the number of AUX cycles in 1 us or 5 us. 5 us should only be used with 1 MHz AUXHFRCO band.
Page 48: Dma - Dma Controller
...the world's most energy friendly microcontrollers 8 DMA - DMA Controller Quick Facts What? 0 1 2 3 The DMA controller can move data without CPU intervention, effectively reducing the energy consumption for a data transfer. Why? The DMA can perform data transfers more Flash energy efficiently than the CPU and allows autonomous operation in low energy modes.
Page 49: Block Diagram
...the world's most energy friendly microcontrollers • Ping-pong (switching between the primary or alternate DMA descriptors, for continuous data flow to/from peripherals) • Scatter-gather (using the primary descriptor to configure the alternate descriptor) • Each channel has a programmable transfer length •...
Page 50: Functional Description
...the world's most energy friendly microcontrollers • A channel select block routing the right peripheral request to each DMA channel 8.4 Functional Description The DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data.
Page 51 ...the world's most energy friendly microcontrollers The controller provides four bits that configure how many AHB bus transfers occur before it re-arbitrates. These bits are known as the R_power bits because the value you enter, R, is raised to the power of two and this determines the arbitration rate.
Page 52 ...the world's most energy friendly microcontrollers Channel Priority level Descending order of number setting channel priority High High High High High High High High High High High Default Default Default Default Default Default Default Default Default Default Default Default Lowest-priority DMA channel After a DMA transfer completes, the controller polls all the DMA channels that are available.
Page 53: Dma Cycle Types
...the world's most energy friendly microcontrollers Figure 8.2. Polling flowchart Start polling Is there a channel request ? Are any channel requests using a high priority- level ? Select channel that has Select channel that has the lowest channel the lowest channel num ber and is set to num ber high priority- level...
Page 54 ...the world's most energy friendly microcontrollers 8.4.2.3.1 Invalid After the controller completes a DMA cycle it sets the cycle type to invalid, to prevent it from repeating the same DMA cycle. 8.4.2.3.2 Basic In this mode, you configure the controller to use either the primary or the alternate data structure. After you enable the channel C and the controller receives a request for this channel, then the flow for this DMA cycle is as follows: 1.
Page 55 ...the world's most energy friendly microcontrollers Figure 8.3. Ping-pong example Task A: Prim ary, cycle_ctrl = b011, 2 = 4, N = 6 Task A Request Request dma_done[C] Task B: Alternate, cycle_ctrl = b011, 2 = 4, N = 12 Task B Request Request...
Page 56 ...the world's most energy friendly microcontrollers 9. The controller performs four DMA transfers. 10. T he controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority. 11. T he controller performs the remaining four DMA transfers. 12.
Page 57: Channel_Cfg For A Primary Data Structure, In Memory Scatter-Gather Mode
...the world's most energy friendly microcontrollers using the primary data structure. The controller continues to switch from primary to alternate to primary… until either: • the host processor configures the alternate data structure for a basic cycle • it reads an invalid data structure. Note After the controller completes the N primary transfers it invalidates the primary data structure by setting the cycle_ctrl field to b000.
Page 58: Memory Scatter-Gather Example
...the world's most energy friendly microcontrollers Figure 8.4. Memory scatter-gather example Initialization: 1. Configure prim ary to enable the copy A, B, C, and D operations: cycle_ctrl = b100, 2 = 4, N = 16. 2. Write the prim ary source data to m em ory, using the structure shown in the following table. src_data_end_ptr dst_data_end_ptr channel_cfg...
Page 59: Channel_Cfg For A Primary Data Structure, In Peripheral Scatter-Gather Mode
...the world's most energy friendly microcontrollers 8. The controller generates an auto-request for the channel and then arbitrates. Task C 9. The controller performs task C. After it completes the task, it generates an auto-request for the channel and then arbitrates. Primary, copy D 10.
Page 60: Peripheral Scatter-Gather Example
...the world's most energy friendly microcontrollers Field Value Description [20:18] src_prot_ctrl Configures the state of HPROT when the controller reads the source data [13:4] n_minus_1 Configures the controller to perform N DMA transfers, where N is a multiple of four next_useburst When set to 1, the controller sets the chnl_useburst_set [C] bit to 1 after the alternate transfer completes...
Page 61 ...the world's most energy friendly microcontrollers Primary, copy A 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A. Task A 2. The controller performs task A. 3. After the controller completes the task it enters the arbitration process. After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy B 4.
Page 62 ...the world's most energy friendly microcontrollers • have a base address that is an integer multiple of the total size of the channel control data structure. Figure 8.6 (p. 62) shows the memory that the controller requires for the channel control data structure, when all 12 channels and the optional alternate data structure are in use.
Page 63 ...the world's most energy friendly microcontrollers Figure 8.7 (p. 63) shows a detailed memory map of the descriptor structure. Figure 8.7. Detailed memory map for the 12 channels, including the alternate data structure Unused 0x 1BC Control Alternate for 0x 1B8 channel 11 Destination End Pointer 0x 1B4...
Page 64: Channel_Cfg Bit Assignments
...the world's most energy friendly microcontrollers Table 8.8. dst_data_end_ptr bit assignments Name Description [31:0] dst_data_end_ptr Pointer to the end address of the destination data Before the controller can perform a DMA transfer, you must program this memory location with the end address of the destination data.
Page 65 ...the world's most energy friendly microcontrollers Name Description You must set dst_size to contain the same value that src_size contains. [27:26] src_inc Set the bits to control the source address increment. The address increment depends on the source data width as follows: Source data width = byte b00 = byte.
Page 66 ...the world's most energy friendly microcontrollers Name Description [13:4] n_minus_1 Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that the DMA cycle contains. You must set these bits according to the size of DMA cycle that you require.
Page 67 ...the world's most energy friendly microcontrollers Name Description When the controller operates in peripheral scatter-gather mode, you must only use this value in the alternate data structure. At the start of a DMA cycle, or 2 DMA transfer, the controller fetches the channel_cfg from system memory.
Page 68 ...the world's most energy friendly microcontrollers Table 8.11. DMA cycle of 12 bytes using a halfword increment Initial values of channel_cfg, prior to the DMA cycle src_size = b00, dst_inc = b01, n_minus_1 = b1011, cycle_ctrl = 1, R_power = b11 End Pointer Count Difference...
Page 69 ...the world's most energy friendly microcontrollers set SRCSTRIDE in DMA_RECT0 to the outer rectangle width of the source, and DSTSTRIDE in DMA_RECT0 to the outer rectangle width of the destination rectangle. Finally, the channel descriptor for channel 0 has to be configured. The source and destination end pointers should be set to the last element of the first line of the source data and destination data respectively.
Page 70: Examples
...the world's most energy friendly microcontrollers in DMA_CTRL. This will prevent the address in the descriptor from being updated. In this case RDSCH0 in DMA_RDS must be set and all other bits in DMA_RDS must be cleared. The bits in DMA_RDS make individual DMA channels remember the source and destination end pointers while active, speeding up their transfers.
Page 71: Register Map
...the world's most energy friendly microcontrollers 8.6 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DMA_STATUS DMA Status Registers 0x004 DMA_CONFIG DMA Configuration Register 0x008 DMA_CTRLBASE Channel Control Data Base Pointer Register 0x00C DMA_ALTCTRLBASE Channel Alternate Control Data Base Pointer Register...
Page 72: Register Description
...the world's most energy friendly microcontrollers 8.7 Register Description 8.7.1 DMA_STATUS - DMA Status Registers Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:16 CHNUM 0x0B...
Page 73 ...the world's most energy friendly microcontrollers Name Reset Access Description CHPROT Channel Protection Control Control whether accesses done by the DMA controller are privileged or not. When CHPROT = 1 then HPROT is HIGH and the access is privileged. When CHPROT = 0 then HPROT is LOW and the access is non-privileged. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 74 ...the world's most energy friendly microcontrollers Name Reset Access Description The base address of the alternate data structure. This register will read as DMA_CTRLBASE + 0x100. 8.7.5 DMA_CHWAITSTATUS - Channel Wait on Request Status Register Offset Bit Position 0x010 Reset Access Name Name...
Page 75 ...the world's most energy friendly microcontrollers 8.7.6 DMA_CHSWREQ - Channel Software Request Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH11SWREQ Channel 11 Software Request Write 1 to this bit to generate a DMA request for this channel.
Page 76 ...the world's most energy friendly microcontrollers 8.7.7 DMA_CHUSEBURSTS - Channel Useburst Set Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH11USEBURSTS RW1H Channel 11 Useburst Set...
Page 77 ...the world's most energy friendly microcontrollers 8.7.8 DMA_CHUSEBURSTC - Channel Useburst Clear Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH11USEBURSTC Channel 11 Useburst Clear Write to 1 to disable useburst setting for this channel.
Page 78 ...the world's most energy friendly microcontrollers 8.7.9 DMA_CHREQMASKS - Channel Request Mask Set Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH11REQMASKS Channel 11 Request Mask Set Write to 1 to disable peripheral requests for this channel.
Page 79 ...the world's most energy friendly microcontrollers 8.7.10 DMA_CHREQMASKC - Channel Request Mask Clear Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH11REQMASKC Channel 11 Request Mask Clear Write to 1 to enable peripheral requests for this channel.
Page 80 ...the world's most energy friendly microcontrollers 8.7.11 DMA_CHENS - Channel Enable Set Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH11ENS Channel 11 Enable Set Write to 1 to enable this channel.
Page 81 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH11ENC Channel 11 Enable Clear Write to 1 to disable this channel. See also description for channel 0. CH10ENC Channel 10 Enable Clear Write to 1 to disable this channel.
Page 82 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to select the alternate structure for this channel. CH8ALTS Channel 8 Alternate Structure Set Write to 1 to select the alternate structure for this channel. CH7ALTS Channel 7 Alternate Structure Set Write to 1 to select the alternate structure for this channel.
Page 83 ...the world's most energy friendly microcontrollers Name Reset Access Description CH5ALTC Channel 5 Alternate Clear Write to 1 to select the primary structure for this channel. CH4ALTC Channel 4 Alternate Clear Write to 1 to select the primary structure for this channel. CH3ALTC Channel 3 Alternate Clear Write to 1 to select the primary structure for this channel.
Page 84 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to obtain high priority for this channel. Reading returns the channel priority status. CH1PRIS Channel 1 High Priority Set Write to 1 to obtain high priority for this channel. Reading returns the channel priority status. CH0PRIS Channel 0 High Priority Set Write to 1 to obtain high priority for this channel.
Page 85 ...the world's most energy friendly microcontrollers 8.7.17 DMA_ERRORC - Bus Error Clear Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ERRORC Bus Error Clear This bit is set high if an AHB bus error has occurred.
Page 86 ...the world's most energy friendly microcontrollers Name Reset Access Description CH5REQSTATUS Channel 5 Request Status When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 DMA transfers.
Page 87 ...the world's most energy friendly microcontrollers Name Reset Access Description When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers. CH5SREQSTATUS Channel 5 Single Request Status When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service...
Page 88 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel. CH4DONE DMA Channel 4 Complete Interrupt Flag Set when the DMA channel has completed its transfer.
Page 89 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to set the corresponding DMA channel complete interrupt flag. CH1DONE DMA Channel 1 Complete Interrupt Flag Set Write to 1 to set the corresponding DMA channel complete interrupt flag. CH0DONE DMA Channel 0 Complete Interrupt Flag Set Write to 1 to set the corresponding DMA channel complete interrupt flag.
Page 90 ...the world's most energy friendly microcontrollers 8.7.23 DMA_IEN - Interrupt Enable register Offset Bit Position 0x100C Reset Access Name Name Reset Access Description DMA Error Interrupt Flag Enable Set this bit to enable interrupt on AHB bus error. 30:12 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 91 ...the world's most energy friendly microcontrollers 8.7.24 DMA_CTRL - DMA Control Register Offset Bit Position 0x1010 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PRDU Prevent Rect Descriptor Update Allows the reuse of a rect descriptor.
Page 92 ...the world's most energy friendly microcontrollers Name Reset Access Description RDSCH5 Retain Descriptor State Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH4 Retain Descriptor State Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration...
Page 93 ...the world's most energy friendly microcontrollers 8.7.27 DMA_LOOP1 - Channel 1 Loop Register Offset Bit Position 0x1024 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DMA Channel 1 Loop Enable Loop enable for channel 1 15:10...
Page 94 ...the world's most energy friendly microcontrollers 8.7.29 DMA_CHx_CTRL - Channel Control Register Offset Bit Position 0x1100 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 21:16 SOURCESEL 0x00...
Page 95 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description SOURCESEL 0b001101 (USART1) 0b0000 USART1RXDATAV USART1RXDATAV REQ/SREQ 0b0001 USART1TXBL USART1TXBL REQ/SREQ 0b0010 USART1TXEMPTY USART1TXEMPTY 0b0011 USART1RXDATAVRIGHT USART1RXDATAVRIGHT REQ/SREQ 0b0100 USART1TXBLRIGHT USART1TXBLRIGHT REQ/SREQ SOURCESEL 0b001110 (USART2) 0b0000 USART2RXDATAV USART2RXDATAV REQ/SREQ 0b0001 USART2TXBL...
Page 96 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description SOURCESEL = 0b101101 (UART1) 0b0000 UART1RXDATAV UART1RXDATAV REQ/SREQ 0b0001 UART1TXBL UART1TXBL REQ/SREQ 0b0010 UART1TXEMPTY UART1TXEMPTY SOURCESEL = 0b110000 (MSC) 0b0000 MSCWDATA MSCWDATA SOURCESEL = 0b110001 (AES) 0b0000 AESDATAWR AESDATAWR 0b0001...
Page 97: Rmu - Reset Management Unit
...the world's most energy friendly microcontrollers 9 RMU - Reset Management Unit Quick Facts What? The RMU ensures correct reset operation. It is responsible for connecting the different 0 1 2 3 reset sources to the reset lines of the EFM32GG.
Page 98 ...the world's most energy friendly microcontrollers up. At startup the EFM32GG loads the stack pointer and program entry point from memory, and starts execution. As seen in Figure 9.1 (p. 98) the Power-on Reset, Brown-out Detectors, Watchdog timeout and RESETn pin all reset the whole system including the Debug Interface. A Core Lockup condition or a System reset request from software resets the whole system except the Debug Interface.
Page 99 ...the world's most energy friendly microcontrollers Table 9.1. RMU Reset Cause Register Interpretation Register Value Cause 0bXXXX XXXX XXXX XXX1 A Power-on Reset has been performed. X bits are don't care. 0bXXXX XXXX 0XXX XX10 A Brown-out has been detected on the unregulated power. 0bXXXX XXXX XXX0 0100 A Brown-out has been detected on the regulated power.
Page 100 ...the world's most energy friendly microcontrollers The BODs are constantly monitoring the voltages. Whenever the unregulated or regulated power drops below the VBODthr value (see Electrical Characteristics for details), or if the AVDD0 or AVDD1 drops below the voltage at the decouple pin (DEC), the corresponding active low BROWNOUTn line is held low.
Page 101 ...the world's most energy friendly microcontrollers 9.3.9 EM4 Wakeup Reset Whenever the system is woken up from EM4 on a pin wake-up request, the EM4WURST bit is set. This bit enables the user to identify that the device was woken up from EM4 using a pin wake-up request. Upon wake-up this bit should be cleared by software.
Page 102: Register Map
...the world's most energy friendly microcontrollers 9.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RMU_CTRL Control Register 0x004 RMU_RSTCAUSE Reset Cause Register 0x008 RMU_CMD Command Register 9.5 Register Description 9.5.1 RMU_CTRL - Control Register Offset Bit Position...
Page 103 ...the world's most energy friendly microcontrollers Name Reset Access Description Set if the Backup BOD sensing on unregulated power triggers. Must be cleared by software. Please see Section 10.3.4.2 (p. 112) for details on how to interpret this bit. BUBODBUVIN Backup Brown Out Detector, BU_VIN Set if the Backup BOD sensing on BU_VIN triggers.
Page 104 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RCCLR Reset Cause Clear Set this bit to clear the LOCKUPRST and SYSREQRST bits in the RMU_RSTCAUSE register. Use the HRCCLR bit in the EMU_AUXCTRL register to clear the remaining bits.
Page 105: Emu - Energy Management Unit
...the world's most energy friendly microcontrollers 10 EMU - Energy Management Unit Quick Facts What? The EMU (Energy Management Unit) handles the different low energy modes in the EFM32GG microcontrollers. Why? The need for performance and peripheral functions varies over time in most 0 1 2 3 applications.
Page 106: Functional Description
...the world's most energy friendly microcontrollers • Low wakeup time 10.3 Functional Description The Energy Management Unit (EMU) is responsible for managing the wide range of energy modes available in EFM32GG. An overview of the EMU module is shown in Figure 10.1 (p. 106) . Figure 10.1.
Page 107 ...the world's most energy friendly microcontrollers Figure 10.2. EMU Energy Mode Transitions Active m ode Low energy m odes No direct transitions between EM1, EM2 or EM3 are available, as can also be seen from Figure 10.2 (p. 107) . Instead, a wakeup will transition back to EM0, in which software can enter any other low energy mode.
Page 108 ...the world's most energy friendly microcontrollers Table 10.1. EMU Energy Mode Overview Wakeup time to EM0 2 µs 2 µs 160 µs MCU clock tree High frequency peripheral clock trees Core voltage regulator High frequency oscillator C full functionality Low frequency peripheral clock trees Low frequency oscillator Real Time Counter LEUART...
Page 109 ...the world's most energy friendly microcontrollers • MCU clock tree is inactive • High frequency peripheral clock trees are active • All peripheral functionality is available 10.3.1.3 EM2 • The high frequency oscillator is inactive • The high frequency peripheral and MCU clock trees are inactive •...
Page 110 ...the world's most energy friendly microcontrollers Table 10.2. EMU Entering a Low Energy Mode Low Energy Mode EM4CTRL EMVREG EM2BLOCK SLEEPDEEP Cortex-M3 Instruction WFI or WFE WFI or WFE Write sequence: 2, 3, 2, 3, 2, 3, 2, 3, 2 (‘x’...
Page 111 ...the world's most energy friendly microcontrollers Table 10.3. EMU Wakeup Triggers from Low Energy Modes Peripheral Wakeup Trigger Any enabled interrupt USART Receive / transmit UART Receive / transmit LEUART Receive / transmit LESENSE Any enabled interrupt Any enabled interrupt Receive address recognition TIMER Any enabled interrupt...
Page 112: Backup Power Domain Overview
...the world's most energy friendly microcontrollers Figure 10.3. Backup power domain overview EFM32 BUCTRL_STATEN BUCTRL_EN BU_STAT Main power BOD BUINACT_PWRCON / BUACT_PWRCON PWRCONF_PWRRES BUBODBUVIN BU_VIN Backup power VDD_DREG Backup Main power power Main supply power supply BUBODVDDDREG STRONG Main dom ain BU_VOUT MEDIUM BUBODUNREG...
Page 113 ...the world's most energy friendly microcontrollers threshold is programmed using BUENRANGE and BUENTHRES in EMU_BUINACT. BUENRANGE decides the voltage range for the BOD, while BUENTHRES is used for tuning of the BOD threshold. Refer to Section 10.3.4.5 (p. 113) for details regarding BOD calibration. Note BUVINPEN in EMU_ROUTE is by default set.
Page 114 ...the world's most energy friendly microcontrollers • Configure the DAC to output to the maximum level and wait for 500 us before configuring the DAC output to the wanted BOD trigger voltage level. • Step through the BOD calibration values (RANGE and THRES in EMU_BUINACT) with 500 us delay in between steps until the BUBODVDDDREG flag in RMU_RSTCAUSE is set.
Page 115 ...the world's most energy friendly microcontrollers • EMU_BUCTRL • EMU_PWRCONF • EMU_BUINACT • EMU_BUACT • EMU_ROUTE Note For registers residing in the CMU and EMU_AUXCTRL, the reset value will be read after exit from EM4 or Backup mode, but if LOCKCONF in EMU_EM4CONF has been set, the locked configuration will be used until LOCKCONF is cleared.
Page 116 ...the world's most energy friendly microcontrollers All the blocks can be turned off except the first one. www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 117: Register Map
...the world's most energy friendly microcontrollers 10.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 EMU_CTRL Control Register 0x004 EMU_MEMCTRL Memory Control Register 0x008 EMU_LOCK Configuration Lock Register 0x024 EMU_AUXCTRL Auxiliary Control Register 0x02C EMU_EM4CONF...
Page 118 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description FULL Full voltage regulator drive strength in EM2 and EM3. 10.5.2 EMU_MEMCTRL - Memory Control Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 119 ...the world's most energy friendly microcontrollers 10.5.4 EMU_AUXCTRL - Auxiliary Control Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) REDLFXOBOOST Reduce LFXO Start-up Boost Current Set this bit to reduce start-up boost current for LFXO.
Page 120 ...the world's most energy friendly microcontrollers Name Reset Access Description Exit EM4 on Backup RTC interrupt. VREGEN EM4 voltage regulator enable When set, the voltage regulator is enabled in EM4, enabling operation of the Backup RTC and retention registers. 10.5.6 EMU_BUCTRL - Backup Power configuration register Offset Bit Position 0x030...
Page 121 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PWRRES Power domain resistor select Select value of series resistor between main power domain and backup power domain. Value Mode Description...
Page 122 ...the world's most energy friendly microcontrollers 10.5.9 EMU_BUACT - Backup mode active configuration register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PWRCON Power connection configuration when in Backup mode Value...
Page 123 ...the world's most energy friendly microcontrollers 10.5.11 EMU_ROUTE - I/O Routing Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) BUVINPEN BU_VIN Pin Enable When set, the BU_VIN pin is enabled.
Page 124 ...the world's most energy friendly microcontrollers 10.5.14 EMU_IFC - Interrupt Flag Clear Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) BURDY Clear Backup functionality ready Interrupt Flag Write to 1 to clear the BURDY interrupt flag.
Page 125 ...the world's most energy friendly microcontrollers Name Reset Access Description Threshold for Backup BOD sensing on BU_VIN. This field is set to the threshold value calibrated during production, hence the reset value might differ from device to device. 10.5.17 EMU_BUBODUNREGCAL - Unregulated power Backup BOD calibration Offset Bit Position...
Page 126: Cmu - Clock Management Unit
...the world's most energy friendly microcontrollers 11 CMU - Clock Management Unit Quick Facts What? The CMU controls oscillators and clocks. EFM32GG supports several different oscillators with minimized power consumption and short start-up time. An additional separate RC oscillator is used for flash 0 1 2 3 programming and debug trace.
Page 127: Functional Description
...the world's most energy friendly microcontrollers • Individual clock prescaler selection for each Low Energy Peripheral • Clock Gating on an individual basis to core modules and all peripherals • Selectable clocks can be output on two pins for use externally. •...
Page 128: Cmu Overview
...the world's most energy friendly microcontrollers Figure 11.1. CMU Overview LESENSE (High frequency tim ing) (Flash Program m ing) AUXCLK AUXHFRCO Tim eout Debug Trace CMU_CTRL_DBGCLK clock switch CMU_HFPERCLKEN0.TIMER0 Clock HFPERCLK TIMER0 Gate CMU_HFPERCLKEN0.TIMER1 HFPERCLK TIMER1 Clock Gate CMU_HFPERCLKDIV.HFPERCLKEN HFPERCLK prescaler CMU_HFPERCLKEN0.I2C0 CMU_HFPERCLKDIV.HFPERCLKDIV...
Page 129 ...the world's most energy friendly microcontrollers choice. To change the selected HFCLK write to HFCLKSEL in CMU_CMD. The HFCLK is running in EM0 and EM1. HFCLK can optionally be divided down by setting HFCLKDIV in CMU_CTRL to a nonzero value. This divides down HFCLK to all high frequency components except the USB Core and is typically used to save energy in USB applications where the system is not required to run at 48 MHz.
Page 130 ...the world's most energy friendly microcontrollers Each Low Energy Peripheral that is clocked by LFACLK has its own prescaler setting and enable bit. The prescaler settings are configured using CMU_LFAPRESC0 and the clock enable bits can be found in CMU_LFACLKEN0. Notice that the LCD has an additional high resolution prescaler for Frame Rate Control, configured by FDIV in CMU_LCDCTRL.
Page 131: Cmu Switching From Hfrco To Hfxo Before Hfxo Is Ready
...the world's most energy friendly microcontrollers There are individual bits for each oscillator indicating the status of the oscillator: • ENABLED - Indicates that the oscillator is enabled • READY - Start-up time is exceeded • SELECTED - Start-up time is exceeded and oscillator is chosen as clock source These status bits are located in the CMU_STATUS register.
Page 132: Cmu Switching From Hfrco To Hfxo After Hfxo Is Ready
...the world's most energy friendly microcontrollers Figure 11.3. CMU Switching from HFRCO to HFXO after HFXO is ready CMU_CMD.HFCLKSEL CMU_OSCENCMD.HFRCOEN CMU_OSCENCMD.HFRCODIS CMU_OSCENCMD.HFXOEN CMU_OSCENCMD.HFXODIS CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_STATUS.HFRCOSEL CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_STATUS.HFXOSEL HFCLK HFRCO HFXO HFXO tim e- out period Switching clock source for LFACLK and LFBCLK is done by setting the LFA and LFB fields in CMU_LFCLKSEL.
Page 133 ...the world's most energy friendly microcontrollers Figure 11.5. LFXO Pin Connection LFXTAL_N LFXTAL_P 32.768kHz It is possible to connect an external clock source to HFXTAL_N/LFXTAL_N pin of the HFXO or LFXO oscillator. By configuring the HFXOMODE/LFXOMODE fields in CMU_CTRL, the HFXO/LFXO can be bypassed.
Page 134: Continuous Calibration (Cont=1)
...the world's most energy friendly microcontrollers Figure 11.6. HW-support for RC Oscillator Calibration DOWNCLK Dom ain Reload down- counter with top value in continouous m ode. CMU_CALCTRL.DOWNSEL AUXHFRCO HFRCO Write top- value using LFRCO DOWNCLK CMU_CALCNT before 20- bit down- counter HFXO starting calibration.
Page 135: Configuration For Operating Frequencies
...the world's most energy friendly microcontrollers 11.3.4 Configuration For Operating Frequencies The HFXO is capable of driving crystals up to 48 MHz, which allows the EFM32 to run at up to this frequency. Different frequencies have different requirements as shown in Table 11.1 (p. 135) . Before going to a high frequency, make sure the registers in the table have the correct values.
Page 136: Register Map
...the world's most energy friendly microcontrollers 11.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CMU_CTRL CMU Control Register 0x004 CMU_HFCORECLKDIV High Frequency Core Clock Division Register 0x008 CMU_HFPERCLKDIV High Frequency Peripheral Clock Division Register 0x00C CMU_HFRCOCTRL HFRCO Control Register...
Page 137: Register Description
...the world's most energy friendly microcontrollers 11.5 Register Description 11.5.1 CMU_CTRL - CMU Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) HFLE High-Frequency LE Interface allow...
Page 138 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 8CYCLES Timeout period of 8 cycles. 1KCYCLES Timeout period of 1024 cycles. 16KCYCLES Timeout period of 16384 cycles. 32KCYCLES Timeout period of 32768 cycles. LFXOBUFCUR LFXO Boost Buffer Current This value has been updated to the correct level during calibration and should not be changed.
Page 139 ...the world's most energy friendly microcontrollers Name Reset Access Description Set this to configure the external source for the HFXO. The oscillator setting takes effect when 1 is written to HFXOEN in CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to HFXODIS in CMU_OSCENCMD. Value Mode Description...
Page 140 ...the world's most energy friendly microcontrollers 11.5.3 CMU_HFPERCLKDIV - High Frequency Peripheral Clock Division Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) HFPERCLKEN HFPERCLK Enable Set to enable the HFPERCLK.
Page 141 ...the world's most energy friendly microcontrollers Name Reset Access Description 10:8 BAND HFRCO Band Select Write this field to set the frequency band in which the HFRCO is to operate. When changing this setting there will be no glitches on the HFRCO output, hence it is safe to change this setting even while the system is running on the HFRCO.
Page 142 ...the world's most energy friendly microcontrollers Name Reset Access Description 10:8 BAND AUXHFRCO Band Select Write this field to set the frequency band in which the AUXHFRCO is to operate. When changing this setting there will be no glitches on the AUXHFRCO output, hence it is safe to change this setting even while the system is using the AUXHFRCO. To ensure an accurate frequency, the AUXTUNING value should also be written when changing the frequency band.
Page 143 ...the world's most energy friendly microcontrollers 11.5.8 CMU_CALCNT - Calibration Counter Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19:0 CALCNT 0x00000...
Page 144 ...the world's most energy friendly microcontrollers Name Reset Access Description Disables the HFXO. HFXOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRXO if this oscillator is selected as the source for HFCLK. HFXOEN HFXO Enable Enables the HFXO. HFRCODIS HFRCO Disable Disables the HFRCO.
Page 145 ...the world's most energy friendly microcontrollers 11.5.11 CMU_LFCLKSEL - Low Frequency Clock Select Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LFBE Clock Select for LFB Extended This bit redefines the meaning of the LFB field.
Page 146 ...the world's most energy friendly microcontrollers 11.5.12 CMU_STATUS - Status Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) USBCLFRCOSEL USBC LFRCO Selected LFRCO is selected (and active) as HFCORECLK...
Page 147 ...the world's most energy friendly microcontrollers Name Reset Access Description HFRCO is enabled and start-up time has exceeded. HFRCOENS HFRCO Enable Status HFRCO is enabled. 11.5.13 CMU_IF - Interrupt Flag Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:8...
Page 148 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) USBCHFCLKSEL USBC HFCLK Selected Interrupt Flag Set Write to 1 to set the USBC HFCLK Selected Interrupt Flag. CALOF Calibration Overflow Interrupt Flag Set Write to 1 to set the Calibration Overflow Interrupt Flag.
Page 149 ...the world's most energy friendly microcontrollers Name Reset Access Description HFRCORDY HFRCO Ready Interrupt Flag Clear Write to 1 to clear the HFRCO Ready Interrupt Flag. 11.5.16 CMU_IEN - Interrupt Enable Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description...
Page 150 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) External Bus Interface Clock Enable Set to enable the clock for EBI. Low Energy Peripheral Interface Clock Enable Set to enable the clock for LE.
Page 151 ...the world's most energy friendly microcontrollers Name Reset Access Description TIMER3 Timer 3 Clock Enable Set to enable the clock for TIMER3. TIMER2 Timer 2 Clock Enable Set to enable the clock for TIMER2. TIMER1 Timer 1 Clock Enable Set to enable the clock for TIMER1. TIMER0 Timer 0 Clock Enable Set to enable the clock for TIMER0.
Page 152 ...the world's most energy friendly microcontrollers Name Reset Access Description Used to check the synchronization status of CMU_LFAPRESC0. Value Description CMU_LFAPRESC0 is ready for update. CMU_LFAPRESC0 is busy synchronizing new value. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LFACLKEN0 Low Frequency A Clock Enable 0 Busy Used to check the synchronization status of CMU_LFACLKEN0.
Page 153 ...the world's most energy friendly microcontrollers Name Reset Access Description Liquid Crystal Display Controller Clock Enable Set to enable the clock for LCD. LETIMER0 Low Energy Timer 0 Clock Enable Set to enable the clock for LETIMER0. Real-Time Counter Clock Enable Set to enable the clock for RTC.
Page 154 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DIV16 LFACLK = LFACLK/16 DIV32 LFACLK = LFACLK/32 DIV64 LFACLK = LFACLK/64 DIV128 LFACLK = LFACLK/128 11:8 LETIMER0 Low Energy Timer 0 Prescaler Configure Low Energy Timer 0 prescaler Value Mode Description...
Page 155 ...the world's most energy friendly microcontrollers 11.5.24 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LEUART1 Low Energy UART 1 Prescaler Configure Low Energy UART 1 prescaler...
Page 156 ...the world's most energy friendly microcontrollers Name Reset Access Description PCNT2CLKEN PCNT2 Clock Enable This bit enables/disables the clock to the PCNT. Value Description PCNT2 is disabled. PCNT2 is enabled. PCNT1CLKSEL PCNT1 Clock Select This bit controls which clock that is used for the PCNT. Value Mode Description...
Page 157 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DIV64 Voltage Boost update Frequency = LFACLK/64. DIV128 Voltage Boost update Frequency = LFACLK/128. VBOOSTEN Voltage Boost Enable This bit enables/disables the VBOOST function. FDIV Frame Rate Control These bits controls the framerate according to this formula: LFACLK = LFACLK / (1 + FDIV).
Page 158 ...the world's most energy friendly microcontrollers Name Reset Access Description 15:0 LOCKKEY 0x0000 Configuration Lock Key Write other value than unlock code lock CMU_CTRL, CMU_HFCORECLKDIV, CMU_HFPERCLKDIV, CMU_HFRCOCTRL, CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_OSCENCMD, CMU_CMD, CMU_LFCLKSEL, CMU_HFCORECLKEN0, CMU_HFPERCLKEN0, CMU_LFACLKEN0, CMU_LFBCLKEN0, CMU_LFAPRESC0, CMU_LFBPRESC0, and CMU_PCNTCTRL from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled.
Page 159: Wdog - Watchdog Timer
...the world's most energy friendly microcontrollers 12 WDOG - Watchdog Timer Quick Facts What? The WDOG (Watchdog Timer) resets the system in case of a fault condition, and can 0 1 2 3 be enabled in all energy modes as long as the low frequency clock source is available.
Page 160: Wdog Timeout Equation
...the world's most energy friendly microcontrollers 12.3.1 Clock Source Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOG_CTRL. The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOG_CTRL can be written to prevent accidental disabling of the selected clocks.
Page 161: Register Map
...the world's most energy friendly microcontrollers 12.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 WDOG_CTRL Control Register 0x004 WDOG_CMD Command Register 0x008 WDOG_SYNCBUSY Synchronization Busy Register 12.5 Register Description 12.5.1 WDOG_CTRL - Control Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 162 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SWOSCBLOCK Software Oscillator Disable Block Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 will turn on the selected WDOG oscillator if it is not already running.
Page 163 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CLEAR Watchdog Timer Clear Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout. Value Mode Description...
Page 164: Prs - Peripheral Reflex System
...the world's most energy friendly microcontrollers 13 PRS - Peripheral Reflex System Quick Facts What? 0 1 2 3 The PRS (Peripheral Reflex System) allows configurable, fast and autonomous communication between the peripherals. Why? Events and signals from one peripheral can be used as input signals or triggers by other peripherals and ensure timing-critical Tim er...
Page 165: Prs Overview
...the world's most energy friendly microcontrollers 13.3.1 Asynchronous Mode Many reflex signals can operate in two modes, synchronous or asynchronous. A synchronous reflex is clocked on HFPERCLK, and can be used as an input to all reflex consumers, but since they require HFPERCLK, they will not work in EM2/EM3.
Page 166 ...the world's most energy friendly microcontrollers Table 13.1. Reflex Producers Module Reflex Output Output Format Async Support ACMP Comparator Output Level Single Conversion Done Pulse Scan Conversion Done Pulse Channel 0 Conversion Pulse Done Channel 1 Conversion Pulse Done GPIO Pin 0 Input Level Pin 1 Input...
Page 167 ...the world's most energy friendly microcontrollers Module Reflex Output Output Format Async Support USART TX Complete Pulse RX Data Received Pulse IrDA Decoder Output Level VCMP Comparator Output Level LESENSE SCANRES register Level Decoder Output Level/Pulse BURTC Overflow Pulse Compare match 0 Pulse Start of Frame Start of Fram Sent/...
Page 168 ...the world's most energy friendly microcontrollers Module Reflex Input Input Format Async Support S1 input Level LESENSE Start scan Pulse/Level Decoder Bit 0 Level Decoder Bit 1 Level Decoder Bit 2 Level Decoder Bit 3 Level Note It is possible to output prs channel 0 - channel 3 onto the GPIO by setting CH0PEN, CH1PEN, CH2PEN, or CH3PEN in the PRS_ROUTE register.
Page 169: Register Map
...the world's most energy friendly microcontrollers 13.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PRS_SWPULSE Software Pulse Register 0x004 PRS_SWLEVEL Software Level Register 0x008 PRS_ROUTE I/O Routing Register 0x010 PRS_CH0_CTRL Channel Control Register PRS_CHx_CTRL...
Page 170 ...the world's most energy friendly microcontrollers Name Reset Access Description CH1PULSE Channel 1 Pulse Generation See bit 0. CH0PULSE Channel 0 Pulse Generation Write to 1 to generate one HFPERCLK cycle high pulse. This pulse is XOR'ed with the corresponding bit in the SWLEVEL register and the selected PRS input signal to generate the channel output.
Page 171 ...the world's most energy friendly microcontrollers 13.5.3 PRS_ROUTE - I/O Routing Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 LOCATION I/O Location...
Page 172 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description POSEDGE A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal NEGEDGE A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal BOTHEDGES A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal...
Page 173 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 0b001 ADC0SCAN ADC scan conversion done ADC0SCAN SOURCESEL 0b010000 (USART0) 0b000 USART0IRTX USART 0 IRDA out USART0IRTX 0b001 USART0TXC USART 0 TX complete USART0TXC 0b010 USART0RXDATAV USART 0 RX Data Valid USART0RXDATAV SOURCESEL 0b010001 (USART1)
Page 174 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 0b000 GPIOPIN0 GPIO pin 0 GPIOPIN0 0b001 GPIOPIN1 GPIO pin 1 GPIOPIN1 0b010 GPIOPIN2 GPIO pin 2 GPIOPIN2 0b011 GPIOPIN3 GPIO pin 3 GPIOPIN3 0b100 GPIOPIN4 GPIO pin 4 GPIOPIN4 0b101 GPIOPIN5 GPIO pin 5 GPIOPIN5...
Page 175: Ebi - External Bus Interface
...the world's most energy friendly microcontrollers 14 EBI - External Bus Interface Quick Facts What? The EBI is used for accessing external parallel devices. The devices appear as a part of the EFM32GG's internal memory map 0 1 2 3 and are therefore extremely simple to use.
Page 176: Functional Description
...the world's most energy friendly microcontrollers • Programmable bus timing (frequency, setup and hold timing) • Individual active high / active low setting of interface control signals • Frame buffer can be either on-chip or off-chip • Alpha-blending and masking 14.3 Functional Description An overview of the EBI module is shown in Figure 14.1 (p.
Page 177: Ebi Overview
...the world's most energy friendly microcontrollers Figure 14.1. EBI Overview EBI_A[27:0] EBI_AD[15:0] Mem ory Interface EBI_WEn Data/ Address EBI_REn EBI_BLn[1:0] CONTROL EBI_CSn[3:0] EBI_ARDY Tim ing EBI_ALE Polarity EBI_NANDWEn MODE EBI_NANDREn EBI_DCLK TFT Interface EBI_DATAEN TFT CONTROL EBI_VSYNC EBI_HSYNC TFT Tim ing EBI_CSTFTn TFT Polarity TFT Size...
Page 178: Ebi Non-Multiplexed 8-Bit Data, 8-Bit Address Read Operation
...the world's most energy friendly microcontrollers Figure 14.2. EBI Non-multiplexed 8-bit Data, 8-bit Address Read Operation RDSETUP RDSTRB RDHOLD (0, 1, 2, ...) (1, 2, 3, ...) (0, 1, 2, ...) EBI_AD[15:8] ADDR[7:0] EBI_AD[7:0] DATA[7:0] EBI_CSn EBI_REn Figure 14.3. EBI Non-multiplexed 8-bit Data, 8-bit Address Write Operation WRSTRB WRHOLD WRSETUP...
Page 179: Ebi Multiplexed 16-Bit Data, 16-Bit Address Read Operation
...the world's most energy friendly microcontrollers Figure 14.4. EBI Address Latch Setup EBI_AD ADDR Latch Ex ternal Async. (MCU) Device DATA Control At the start of the transaction the address is output on the EBI_AD lines. The Latch is controlled by the ALE (Address Latch Enable) signal and stores the address.
Page 180: Ebi Multiplexed 8-Bit Data, 24-Bit Address Read Operation
...the world's most energy friendly microcontrollers Figure 14.7. EBI Multiplexed 8-bit Data, 24-bit Address Read Operation ADDRSETUP RDSETUP RDSTRB RDHOLD (0, 1, 2, ...) (1, 2, 3, ...) (0, 1, 2, ...) (1, 2, 3, ...) EBI_AD[15:8] ADDR[23:16] ADDR[7:0] EBI_AD[7:0] ADDR[15:8] DATA[7:0] EBI_ALE...
Page 181: Ebi Non-Multiplexed 16-Bit Data Read Operation With Extended Address
...the world's most energy friendly microcontrollers Figure 14.9. EBI Non-multiplexed 16-bit Data Read Operation with Extended Address RDSETUP RDSTRB RDHOLD (0, 1, 2, ...) (1, 2, 3, ...) (0, 1, 2, ...) EBI_A[N- 1:0] ADDR[N:1] EBI_AD[15:0] DATA[15:0] EBI_CSn EBI_REn Figure 14.10. EBI Non-multiplexed 16-bit Data Write Operation with Extended Address WRSTRB WRHOLD WRSETUP...
Page 182: Ebi Page Mode Read Operation For D8A8 Addressing Mode
...the world's most energy friendly microcontrollers Table 14.1. EBI Intrapage hit condition for read on address Addr (non-mentioned Addr bits are unchanged) PAGELEN, INCHIT 8-bit External Device 16-bit External Device PAGELEN=MEMBER4, INCHIT=0 Addr[1:0] changed Addr[2:0] changed PAGELEN=MEMBER8, INCHIT=0 Addr[2:0] changed Addr[3:0] changed PAGELEN=MEMBER16, INCHIT=0 Addr[3:0] changed...
Page 183: Ebi Page Mode Read Operation For D8A24Ale Addressing Mode
...the world's most energy friendly microcontrollers Figure 14.13. EBI Page Mode Read Operation for D8A24ALE addressing mode ADDRSETUP RDSETUP RDSTRB RDPA RDPA RDPA RDHOLD (0, 1, 2, ...) (0, 1, 2, ...) (1, 2, 3, ...) (1, 2, 3, ...) (1, 2, 3, ...) (1, 2, 3, ...) (0, 1, 2, ...)
Page 184: Ebi 16-Bit Data Multiplexed Read Operation Using Extended Addressing
...the world's most energy friendly microcontrollers EBI_CTRL register to D16A16ALE and by enabling the required address lines via the ALB and APEN bitfields of the EBI_ROUTE register. Figure 14.16. EBI Extended Address Latch Setup EBI_A ADDR MSBs EBI_AD ADDR LSBs Latch Ex ternal Async.
Page 185 ...the world's most energy friendly microcontrollers respectively. For example, in case all memory banks use the 8-bit addressing mode D8A8, then the lower 8 address bits are always output on EBI_AD. Therefore, if address extension is required, only address bits 8 and upwards need to be enabled on EBI_A. This is done by setting the EBI_A lower bound to 8 by setting ALB to A8 in EBI_ROUTE and by enabling the required higher address lines via the APEN bitfield in EBI_ROUTE.
Page 186: Ebi Multiplexed Read Operation With Reduced Length Strobes
...the world's most energy friendly microcontrollers the trailing edge of the strobe can be moved half a clock period earlier. In case of EBI_REn, EBI_WEn, EBI_NANDREn and EBI_NANDWEn the leading edge of the strobe can be moved half a clock period later.
Page 187 ...the world's most energy friendly microcontrollers • Between two external device transactions in case the NOIDLE/NOIDLEn bit is 0. • Between two external device transactions to different banks. • When no request for an external transaction is available in the EBI. A RDHOLDX cycle will automatically get inserted for the following case: •...
Page 188 ...the world's most energy friendly microcontrollers When ITS is set to 1 each memory bank uses an individual timing set. In this case registers EBI_ADDRTIMING, EBI_RDTIMING and EBI_WRTIMING only apply to bank 0. Timing for bank n is then defined in the EBI_ADDRTIMINGn, EBI_RDTIMINGn and EBI_WRTIMINGn registers. Note All timing related bitfields have a default value which is equal to the highest possible value for these bitfields, which makes the default values a better fit for slow memory devices.
Page 189 ...the world's most energy friendly microcontrollers 14.3.12 Bank Access The EBI is split in 4 different address regions, each connected to an individual EBI_CSn line. When accessing one of the memory regions, the corresponding CSn line is asserted. This way up to 4 separate devices can share the EBI lines and be identified by the EBI_CSn line.
Page 190 ...the world's most energy friendly microcontrollers Figure 14.23. EBI Default Memory Map (ALTMAP = 0) 0 xffffffff 0 xc0 0 0 0 0 0 0 0 xbfffffff 0 x8 fffffff EBI Region 3 (64 MB) 0 x8 c0 0 0 0 0 0 0 x8 bffffff EBI Regions EBI Region 2 (64 MB)
Page 191 ...the world's most energy friendly microcontrollers Figure 14.24. EBI Alternative Memory Map (ALTMAP = 1) 0 xffffffff 0 xbfffffff EBI Region 3 (256 MB) 0 xc0 0 0 0 0 0 0 0 xbfffffff 0 xb0 0 0 0 0 0 0 0 xafffffff EBI Regions EBI Region 2 (256 MB)
Page 192: Ebi Connection With Standard Nand Flash
...the world's most energy friendly microcontrollers 14.3.14 NAND Flash Support NAND Flash devices offer high density at relatively low cost when compared to NOR Flash devices. Unlike NOR Flash, which offers random read access, NAND Flash devices are based on page access and use an indirect interface.
Page 193: Ebi Connection With Chip Enable Don't Care Nand Flash
...the world's most energy friendly microcontrollers Figure 14.26. EBI Connection with Chip Enable Don't Care NAND Flash EBI_CSn EBI_A[25] EBI_A[24] EBI_NANDREn EBI_NANDWEn CE don’t care (MCU) NAND Flash EBI_AD[] IO[] GPIO GPIO R/ B Note • (0) For a standard NAND Flash the EBI_CSn should be left unconnected. •...
Page 194 ...the world's most energy friendly microcontrollers the number of address cycles are not configured in the EBI and need to be dealt with via driver software. Also higher level tasks as for example wear-leveling, bad block management, and logical-to-physical block mapping should be addressed via driver software. External transaction width is defined via the address mode as defined in MODE field of EBI_CTRL.
Page 195: Ebi Nand Flash Data Input Timing
...the world's most energy friendly microcontrollers Figure 14.29. EBI NAND Flash Data Input Timing WRSETUP WRSTRB WRHOLD (0, 1, 2, ...) (1, 2, 3, ...) (0, 1, 2, ...) EBI_AD[x ] = NAND ALE EBI_AD[y] = NAND CLE EBI_AD[7:0] = NAND IO DATA IN GPIO or EBI_CSn = NAND CEn EBI_NANDWEn = NAND WEn...
Page 196: Ebi Nand Flash Data Output Timing
...the world's most energy friendly microcontrollers Figure 14.30. EBI NAND Flash Data Output Timing RDSTRB RDSETUP RDHOLD (1, 2, 3, ...) (0, 1, 2, ...) (0, 1, 2, ...) RHOH EBI_AD[7:0] = NAND IO DATA OUT GPIO or EBI_CSn = NAND CEn EBI_NANDWEn = NAND REn GPIO = NAND R/ B The EBI_RDTIMING(n) setting requirements for satisfying the NAND Flash timing parameters for data...
Page 197 ...the world's most energy friendly microcontrollers register to D8A8 indicating that the attached device is 8-bit wide. Program the EBI_RDTIMING and EBI_WRTIMING registers to fulfill the NAND timing requirements. • Command and address phase: Program the NAND Command register to the page read command and program the NAND Address register to the required read address.
Page 198: Ebi Ecc Generation
...the world's most energy friendly microcontrollers The ECC computation is as shown in Figure 14.31 (p. 198) and Table 14.8 (p. 198) . Although the table only shows the ECC generation for 8-bit data transfers, the ECC hardware also works for 16-bit data transfers.
Page 199: Ebi Ebi_Eccparity Format
...the world's most energy friendly microcontrollers The generated ECC code can be read from the EBI_ECCPARITY register according to the format shown in Figure 14.32 (p. 199) . The number of valid ECC bits depends on the number of transferred bytes during the time that the ECC hardware is running as indicated in Table 14.10 (p.
Page 200: Ebi Tft Total Width
...the world's most energy friendly microcontrollers 14.3.16 TFT Direct Drive TFT Direct Drive can be used to automatically transfer frame data stored in either internal or external memory to a TFT display without frame buffer. The EBI generates the necessary RGB control signals for the TFT display and it coordinates and aligns the pixel data transfers accordingly.
Page 201: Ebi Tft Size
...the world's most energy friendly microcontrollers Figure 14.33. EBI TFT Size HSYNC+ 1 HCNT = 0 HCNT = HBPORCH+ HSZ+ HFPORCH VCNT = 0 VCNT = 0 HSZ+ 1 HBPORCH HFPORCH Visible Display HCNT = 0 HCNT = HBPORCH+ HSZ+ HFPORCH VCNT = VBPORCH+ VSZ+ VFPORCH VCNT = VBPORCH+ VSZ+ VFPORCH Total width = HBPORCH + (HSZ + 1) + HFPORCH...
Page 202: Ebi Tft Direct Drive From Internal Memory
...the world's most energy friendly microcontrollers If INTERLEAVE is limited to PORCH only and zero porch sizes are programmed in the EBI_TFTHPORCH and EBI_TFTVPORCH registers, then no slots are left open for interleaving traffic and therefore interleaving EBI accesses can never finish. 14.3.16.1 Direct Drive from Internal Memory Any internal memory can be used as the frame source location for Direct Drive.
Page 203: Ebi Tft Direct Drive From External Memory (Non-Multiplexed Address/Data)
...the world's most energy friendly microcontrollers Figure 14.35. EBI TFT Direct Drive from External Memory (non-multiplexed address/data) Control Ex ternal Mem ory EBI_A ADDR Device DATA EBI_AD (MCU) DATA EBI_DCLK EBI_DATAEN EBI_VSYNC, EBI_HSYNC EBI_TFTCSn Figure 14.36. EBI TFT Direct Drive from External Memory (multiplexed address/data) Control EBI_ALE Ex ternal...
Page 204 ...the world's most energy friendly microcontrollers the EBI_TFTFRAMEBASE register is copied into an internal frame base buffer (FBC). This allows software to reprogram the EBI_TFTFRAMEBASE register based on VSYNC or HSYNC interrupts, which in turn can be used to for example implement double buffering or scrolling schemes. The HSYNC and VSYNC interrupts are generated at the same time as the local copy of EBI_TFTFRAMEBASE is made.
Page 205: Ebi Alpha Blending Equation
...the world's most energy friendly microcontrollers Figure 14.38. EBI TFT Alpha Blending and Masking AHB WDATA EBI_TFTMASK EBI_TFTPIXEL0 EBI_TFTALPHA EBI_TFTPIXEL1 ex ternal Mask Check m ask m atch COLOR1SRC COLOR0 COLOR1 Alpha Blend blend m ask m atch EBI_TFTPIXEL EBI_AD EBI_AD ex ternal = (MASKBLEND = = EMASK) or (MASKBLEND = = EALPHA) or (MASKBLEND = = EMASKEALPHA) blend = (MASKBLEND = = IALPHA) or (MASKBLEND = = EALPHA)
Page 206: Ebi In-Place Alpha Blending Into External Memory
...the world's most energy friendly microcontrollers Color0 source selection is based on the MASKBLEND bitfield of the EBI_TFTCTRL register. Internal write data is used for MASKBLEND settings equal to IMASK, IALPHA, or IMASKIALPHA. External write data is used for MASKBLEND settings equal to EMASK, EALPHA, or EMASKEALPHA. The RGB data for Color1 is read from either the BANKSEL memory bank or from the EBI_TFTPIXEL1 register as defined in the COLOR1SRC bitfield of the EBI_TFTCTRL register.
Page 207 ...the world's most energy friendly microcontrollers transfer is suppressed. The resulting image in the frame buffer will keep its original background around the corners of the icon. External masking is enabled by setting the EMASK bit in the EBI_TFTCTRL register to 1. If enabled, writes to the memory bank defined in the BANKSEL bitfield of the EBI_TFTCTRL register are suppressed in case the write data matches the value in EBI_TFTMASK.
Page 208: Ebi Tft Pixel Timing
...the world's most energy friendly microcontrollers Figure 14.39. EBI TFT Pixel Timing DCLKPERIOD DCLKPERIOD (1, 2, 3, ...) (1, 2, 3, ...) EBI_DCLK EBI_AD[15:0] PIXEL N+ 1 PIXEL N TFTSETUP TFTHOLD TFTSETUP TFTHOLD (0, 1, 2, ...) (0, 1, 2, ...) (0, 1, 2, ...) (0, 1, 2, ...) When driving the TFT from internal memory, the TFT timing is defined in the EBI_TFTTIMING register...
Page 209: Ebi Tft Pixel Timing: Ebi_Dclk Driven Off Positive Edge Internal Clock
...the world's most energy friendly microcontrollers Figure 14.42. EBI TFT Horizontal Porch Timing HBPORCH HFPORCH (0, 1, 2, ...) (1, 2, 3, ...) (0, 1, 2, ...) EBI_DCLK EBI_AD[15:0] HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH EBI_DATAEN EBI_HSYNC HSYNCSTART (0, 1, 2, ...) HSYNC (1, 2, 3, ...) The timing parameters related to the vertical timing are shown in Figure 14.43 (p.
Page 210: Ebi Tft Pixel Timing: Ebi_Dclk Driven Off Negative Edge Internal Clock
...the world's most energy friendly microcontrollers Figure 14.45. EBI TFT Pixel Timing: EBI_DCLK driven off Negative Edge Internal Clock INTERNAL CLOCK EBI_DCLK EBI_AD[15:0] PIXEL N TFTSETUP TFTSETUPHOLD TFTHOLD (0, 1, 2, ...) (½ + ½) (0, 1, 2, ...) 14.3.19 Control Signal Polarity It is possible to individually configure the control signals to be active high/low by setting or clearing the appropriate bits in the EBI_POLARITY register.
Page 211 ...the world's most energy friendly microcontrollers Figure 14.46. EBI TFT Interrupts VSYNC, HSYNC HSYNC HSYNC VBPORCH HSZ+ 1 HBPORCH HFPORCH Visible Display HSYNC VFPORCH, HSYNC HSYNC HSYNC HSYNC The DDEMPTY interrupt flag indicates that the EBI_TFTDD register is empty during Direct Drive from internal memory.
Page 212: Register Map
...the world's most energy friendly microcontrollers 14.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 EBI_CTRL Control Register 0x004 EBI_ADDRTIMING Address Timing Register 0x008 EBI_RDTIMING Read Timing Register 0x00C EBI_WRTIMING Write Timing Register 0x010 EBI_POLARITY...
Page 213: Register Description
...the world's most energy friendly microcontrollers Offset Name Type Description 0x0A0 EBI_IFC Interrupt Flag Clear Register 0x0A4 EBI_IEN Interrupt Enable Register 14.5 Register Description 14.5.1 EBI_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description ALTMAP Alternative Address Map Enable This field enables or disables the alternative (256 MB per bank) address map.
Page 214 ...the world's most energy friendly microcontrollers Name Reset Access Description NOIDLE3 No idle cycle insertion on bank 3. Enables or disables idle state insertion between transfers for bank 3. Ignored when ITS = 0. NOIDLE2 No idle cycle insertion on bank 2. Enables or disables idle state insertion between transfers for bank 2.
Page 215 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description D8A8 EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register. D16A16ALE EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register.
Page 216 ...the world's most energy friendly microcontrollers Name Reset Access Description Enables or disables page mode reads. PREFETCH Prefetch Enable Enables or disables prefetching of data from sequential address. HALFRE Half Cycle REn Strobe Duration Enable Enables or disables half cycle duration of the REn strobe in the last RDSTRB cycle. 27:18 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 217 ...the world's most energy friendly microcontrollers 14.5.5 EBI_POLARITY - Polarity Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) BLPOL BL Polarity Sets the polarity of the EBI_BLn lines.
Page 218 ...the world's most energy friendly microcontrollers 14.5.6 EBI_ROUTE - I/O Routing Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 LOCATION I/O Location...
Page 219 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description EBI_A[24:L] pins enabled. EBI_A[25:L] pins enabled. EBI_A[26:L] pins enabled. EBI_A[27:L] pins enabled. 17:16 Sets the lower bound for EBI_A enabling Sets the lower bound of the EBI_A lines which can be enabled in the APEN field. Value Mode Description...
Page 220 ...the world's most energy friendly microcontrollers Name Reset Access Description Enables or disables half cycle duration of the ALE strobe in the last address setup cycle. 27:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ADDRHOLD Address Hold Time Sets the number of cycles the address is held after ALE is asserted.
Page 221 ...the world's most energy friendly microcontrollers 14.5.9 EBI_WRTIMING1 - Write Timing Register 1 Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) WBUFDIS Write Buffer Disable Enables or disables the write buffer.
Page 222 ...the world's most energy friendly microcontrollers Name Reset Access Description Sets the polarity of the EBI_ARDY line. Value Mode Description ACTIVELOW ARDY is active low. ACTIVEHIGH ARDY is active high. ALEPOL Address Latch Polarity Sets the polarity of the EBI_ALE line. Value Mode Description...
Page 223 ...the world's most energy friendly microcontrollers 14.5.12 EBI_RDTIMING2 - Read Timing Register 2 Offset Bit Position 0x02C Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PAGEMODE Page Mode Access Enable Enables or disables page mode reads.
Page 224 ...the world's most energy friendly microcontrollers Name Reset Access Description Enables or disables half cycle duration of the WEn strobe in the last WRSTRB cycle. 27:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 17:16 WRHOLD Write Hold Time...
Page 225 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description ACTIVELOW REn and NANDREn are active low. ACTIVEHIGH REn and NANDREn are active high. CSPOL Chip Select Polarity Sets the polarity of the EBI_CSn line. Value Mode Description ACTIVELOW CSn is active low.
Page 226 ...the world's most energy friendly microcontrollers Name Reset Access Description PAGEMODE Page Mode Access Enable Enables or disables page mode reads. PREFETCH Prefetch Enable Enables or disables prefetching of data from sequential address. HALFRE Half Cycle REn Strobe Duration Enable Enables or disables half cycle duration of the REn strobe in the last RDSTRB cycle.
Page 227 ...the world's most energy friendly microcontrollers 14.5.18 EBI_POLARITY3 - Polarity Register 3 Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) BLPOL BL Polarity Sets the polarity of the EBI_BLn lines.
Page 228 ...the world's most energy friendly microcontrollers 14.5.19 EBI_PAGECTRL - Page Control Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 26:20 KEEPOPEN 0x00...
Page 229 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description BANK2 Memory bank 2 is connected to a NAND Flash device. BANK3 Memory bank 3 is connected to a NAND Flash device. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) NAND Flash control enable This field enables NAND Flash control for the memory bank defined in BANK.
Page 230 ...the world's most energy friendly microcontrollers Name Reset Access Description Indicates that EBI_TFTPIXEL is full. TFTPIXEL1EMPTY EBI_TFTPIXEL1 is empty. Indicates that EBI_TFTPIXEL1 is empty. TFTPIXEL0EMPTY EBI_TFTPIXEL0 is empty. Indicates that EBI_TFTPIXEL0 is empty. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ECCACT EBI ECC Generation Active.
Page 231 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description RGB565 RGB data is 565. RGB555 RGB data is 555. 23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 21:20 BANKSEL Graphics Bank...
Page 232 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description EMASKEALPHA External Masking and Alpha Blending are enabled. TFT Direct Drive Mode This field sets the Direct Mode. Value Mode Description DISABLED Direct Drive is disabled. INTERNAL Direct Drive from internal memory enabled and started.
Page 233 ...the world's most energy friendly microcontrollers 14.5.27 EBI_TFTSTRIDE - TFT Stride Register Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 HSTRIDE 0x000...
Page 234 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 29:28 HSYNCSTART HSYNC Start Delay Sets the HSYNC start position into the horizontal back porch in DCLK cycles. 27:26 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 235 ...the world's most energy friendly microcontrollers 14.5.31 EBI_TFTTIMING - TFT Timing Register Offset Bit Position 0x078 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 29:28 TFTHOLD TFT Hold Time...
Page 236 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description ACTIVEHIGH HSYNC is active high. DATAENPOL TFT DATAEN Polarity Sets the polarity of the EBI_DATAEN line. Value Mode Description ACTIVELOW DATAEN is active low. ACTIVEHIGH DATAEN is active high. DCLKPOL TFT DCLK Polarity Sets the active edge polarity of the EBI_DCLK line.
Page 237 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ALPHA 0x000 TFT Alpha Blending Factor Sets the alpha blending factor. The maximum value is 256. 14.5.35 EBI_TFTPIXEL0 - TFT Pixel 0 Register Offset Bit Position...
Page 238 ...the world's most energy friendly microcontrollers 14.5.37 EBI_TFTPIXEL - TFT Alpha Blending Result Pixel Register Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DATA 0x0000...
Page 239 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DDJIT Direct Drive Jitter Interrupt Flag Set when DCLKPERIOD is not met. DDEMPTY Direct Drive Data Empty Interrupt Flag Set when Direct Drive engine EBI_TFTDD data is empty.
Page 240 ...the world's most energy friendly microcontrollers 14.5.41 EBI_IFC - Interrupt Flag Clear Register Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DDJIT Direct Drive Jitter Interrupt Flag Clear Write to 1 to clear Direct Drive Jitter Interrupt flag.
Page 241 ...the world's most energy friendly microcontrollers Name Reset Access Description Set to enable interrupt on Horizontal Sync interrupt flag. VSYNC Vertical Sync Interrupt Enable Set to enable interrupt on Vertical Sync interrupt flag. www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 242: Usb - Universal Serial Bus Controller
...the world's most energy friendly microcontrollers 15 USB - Universal Serial Bus Controller Quick Facts What? The USB is a full-speed/low-speed USB 2.0 compliant USB Controller that can be used in various OTG Dual Role Device, Host and Device configurations. The on-chip 3.3V regulator delivers up to 50 mA and can also be used to power external components, eliminating the need for an external LDO.
Page 243: Usb System Description
...the world's most energy friendly microcontrollers • SRP detection in EM2 (during host session off) • Soft connect/disconnect • Full OTG support • Compliant with On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification, Revision 2.0 • Compliant with USB On-The-Go Supplement, Revision 1.3 •...
Page 244 ...the world's most energy friendly microcontrollers The system part is accessed using USB registers from offset 0x000 to 0x018 and controls the voltage regulator and enabling/disabling of the PHY and USB pins. This part is clocked by HFCORECLK is accessed using an APB slave interface. The system part can thus be accessed independently of the core part, without HFCORECLK running.
Page 245: Bus-Powered Device
...the world's most energy friendly microcontrollers 15.3.3.1 Bus-powered Device A bus-powered device configuration is shown in Figure 15.2 (p. 245) . In this configuration the voltage regulator powers the PHY and the EFM32 at 3.3 V. The voltage regulator output (USB_VREGO) can also be used to power other components of the system.
Page 246: Self-Powered Device
...the world's most energy friendly microcontrollers 15.3.3.3 Self-powered Device (with bus-power switch) A self-powered device (with bus-power switch) may switch power supply to VBUS when connected to a host. This is typically useful for extending the life of battery-powered devices and enables the use of coin-cell driven systems with low maximum peak current.
Page 247 ...the world's most energy friendly microcontrollers Figure 15.5. OTG Dual Role Device (5V) USB_VREGO USB_VREGI Power switch + over- current detection GPIO (over- current) USB_VBUSEN USB_VBUS VBUS USB_DP USB_DM USB_ID 15.3.3.5 OTG Dual Role Device (5V step-up regulator) An OTG Dual Role Device (5V step-up regulator) configuration is shown in Figure 15.6 (p. 247) . When 5V is not available, an external 5V step-up regulator is needed.
Page 248 ...the world's most energy friendly microcontrollers USB connector which is a USB Standard-A Connector. In host mode, the minimum VBUS decoupling capacitance is 96 uF. In this configuration, the VREGO sense circuit should be left disabled. Figure 15.7. Host 3.0V – 3.6V USB_VREGI USB_VREGO 5V step- up...
Page 249: Usb Core Description
...the world's most energy friendly microcontrollers During suspend, the bias current for the regulator can be reduced if the current requirements in EM2/3 are low. The bias current in EM2/3 is controlled by BIASPROGEM23 in USB_CTRL. When EM2/3 is entered, the bias current for the regulator switches to what is specified in BIASPROGEM23 in USB_CTRL.
Page 250 ...the world's most energy friendly microcontrollers Portions Copyright © 2010 Synopsys, Inc. Used with permission. Synopsys and DesignWare are registered trademarks of Synopsys, Inc. 15.4.1 Overview: Programming the Core Each significant programming feature of the core is discussed in a separate section. This chapter uses abbreviations for register names and their fields.
Page 251 ...the world's most energy friendly microcontrollers 4. Wait for the USB_HPRT.PRTCONNDET interrupt. This indicates that a device is connect to the port. 5. Program the USB_HPRT.PRTRST bit to 1. This starts the reset process. 6. Wait at least 10 ms for the reset process to complete. 7.
Page 252 ...the world's most energy friendly microcontrollers • Periodic Frame Interval 2. Program the USB_GINTMSK register to unmask the following interrupts. • USB Reset • Enumeration Done • Early Suspend • USB Suspend 3. Wait for the USB_GINTSTS.USBRST interrupt, which indicates a reset has been detected on the USB and lasts for about 10 ms.
Page 253 ...the world's most energy friendly microcontrollers 15.4.1.2.3 Device Soft Disconnection The application can perform a soft disconnect by setting the Soft disconnect bit (SFTDISCON) in Device Control Register (USB_DCTL). Send/Receive USB Transfers -> Soft disconnect->Soft reset->USB Device Enumeration Sequence of operations: 1.
Page 254 ...the world's most energy friendly microcontrollers 15.4.2.2.1 Transfer-Level Operation In DMA mode, the application is interrupted only after the programmed transfer size is transmitted or received (provided the core detects no NAK/Timeout/Error response in Host mode, or Timeout/CRC Error in Device mode). The application must handle all transaction errors. In Device mode, all the USB errors are handled by the core itself.
Page 255 ...the world's most energy friendly microcontrollers Figure 15.8. Transmit Transaction-Level Operation in Slave Mode Start Set up the channel/endpoint Write 1 packet to the Transmit FIFO interrupt? Rewrite packet to Get channel/endpoint the Transmit FIFO interrupt status Retry required? Transfer complete? Done Figure 15.9.
Page 256: Host Programming Operations
...the world's most energy friendly microcontrollers 15.4.2.3.2 Pipelined Transaction-Level Operation The application can pipeline more than one transaction (IN or OUT) with pipelined transaction-level operation, which is analogous to Transfer mode in DMA mode. In pipelined transaction-level operation, the application can program the core to perform multiple transactions. The advantage of this mode compared to transaction-level operation is that the application is not interrupted on a packet basis.
Page 257 ...the world's most energy friendly microcontrollers 1. Program the USB_GINTMSK register to unmask the following: 2. Channel Interrupt • Non-periodic Transmit FIFO Empty for OUT transactions (applicable for Slave mode that operates in pipelined transaction-level with the Packet Count field programmed with more than one). •...
Page 258 ...the world's most energy friendly microcontrollers For high-bandwidth interrupt INs in Slave mode, once the application has received a DATATGLERR interrupt it must disable the channel and wait for a Channel Halted interrupt. The application must be able to receive other interrupts (DATATGLERR, NAK, Data, XACTERR, BBLERR) for the same channel before receiving the halt.
Page 259 ...the world's most energy friendly microcontrollers Table 15.1. Host Programming Operations Mode OUT/SETUP Control Slave Bulk and Control IN Transactions in Bulk and Control OUT/SETUP Slave Mode (p. 263) Transactions in Slave Mode (p. 261) Bulk and Control IN Transactions in Bulk and Control OUT/SETUP DMA Mode (p.
Page 260 ...the world's most energy friendly microcontrollers Figure 15.10. Transmit FIFO Write Task in Slave Mode Start Read USB_GNPTXSTS / USB_HPTXFSIZ registers for available FIFO and Queue spaces Wait for 1 MPS USB_GAHBCFG NPTXFEMPLVL or LPS FIFO space available? USB_GAHBCFG PTXFEMPLVL interrupt Write 1 packet data to...
Page 261 ...the world's most energy friendly microcontrollers 15.4.3.6.4 Bulk and Control OUT/SETUP Transactions in Slave Mode To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 250) . Before it can communicate with the connected device, it must initialize a channel as described in Channel Initialization (p.
Page 262: Normal Bulk/Control Out/Setup And Bulk/Control In Transactions In Slave Mode
...the world's most energy friendly microcontrollers Figure 15.12. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in Slave Mode Application Host Device init _ reg(ch_1) Non- Periodic Request init_reg( ch_2) Queue write _tx_fifo Assum e that this queue can ( ch_1) hold 4 entries.
Page 263 ...the world's most energy friendly microcontrollers Transfer Done = 1 Unmask CHHLTD Disable Channel else if (NAK or XACTERR) Rewind Buffer Pointers Unmask CHHLTD Disable Channel if (XACTERR) Increment Error Count Unmask ACK else Reset Error Count else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel...
Page 264 ...the world's most energy friendly microcontrollers 1. Initialize channel 2 as explained in Channel Initialization (p. 256) . 2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Non-periodic Request Queue. 3. The core attempts to send an IN token after completing the current OUT transaction. 4.
Page 265 ...the world's most energy friendly microcontrollers else if (ACK) Reset Error Count Mask ACK else if (DATATGLERR) Reset Error Count 15.4.3.6.6 Control Transactions in DMA Mode Setup, Data, and Status stages of a control transfer must be performed as three separate transfers. Setup- and Data- or Status-stage OUT transactions are performed similarly to the bulk OUT transactions explained in Bulk and Control OUT/SETUP Transactions in DMA Mode (p.
Page 266 ...the world's most energy friendly microcontrollers 2. The Device responds with NAK. 3. If the application has unmasked NAK, the core generates the corresponding interrupt(s) to the application. The application is not required to service these interrupts, since the core takes care of rewinding of buffer pointers and re-initializing the Channel without application intervention.
Page 267: Normal Bulk/Control Out/Setup And Bulk/Control In Transactions In Dma Mode
...the world's most energy friendly microcontrollers Figure 15.13. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in DMA Mode Application Host Device init_reg( ch_1) Non- Periodic Request init_reg( ch_2) Queue Assum e that this queue can hold 4 entries. ch_1 ch_2 ch_1 ch_2 ch_1...
Page 268: Interrupt Service Routine For Bulk/Control Out Transaction In Dma Mode
...the world's most energy friendly microcontrollers Figure 15.14. Interrupt Service Routine for Bulk/Control OUT Transaction in DMA Mode Start Unm asked the required USB_HAINTMSK and USB_HCx _INTMSK status bits Interrupt Read USB_HAINT to determ ine the channel which caused the Interrupt and read the corresponding USB_HCx _INT USB_HCx _INT.
Page 269 ...the world's most energy friendly microcontrollers must read the NAK/ACK along with the xact_err. If NAK/ACK is not set, the Xact_err count must be incremented otherwise application must initialize the Xact_err count to 1. Bulk/Control OUT/SETUP Unmask (CHHLTD) if (CHHLTD) if (XFERCOMPL or STALL) Reset Error Count (Error_count=1) Mask ACK...
Page 270 ...the world's most energy friendly microcontrollers 3. The Non-periodic Request Queue depth = 4. 15.4.3.6.8.1 Normal Bulk and Control IN Operations The sequence of operations in Figure 15.13 (p. 267) is as follows: 1. Initialize and enable channel 2 as explained in Channel Initialization (p. 256) . 2.
Page 271 ...the world's most energy friendly microcontrollers 15.4.3.6.9 Interrupt OUT Transactions in Slave Mode To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 250) . Before it can communicate with the connected device, it must initialize a channel as described in Channel Initialization (p.
Page 272: Normal Interrupt Out/In Transactions In Slave Mode
...the world's most energy friendly microcontrollers Figure 15.15. Normal Interrupt OUT/IN Transactions in Slave Mode Host Device Application init_reg( ch_1) init _ reg(ch_2) Periodic Request Queue Assum e that this queue write _tx_fifo can hold 4 entries . (ch_1) set_ch_en ch_1 ( ch_2) ch_2...
Page 273 ...the world's most energy friendly microcontrollers else if (NAK or XACTERR) Rewind Buffer Pointers Reset Error Count Mask ACK Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 Frame) else if (ACK) Reset Error Count Mask ACK...
Page 274 ...the world's most energy friendly microcontrollers 5. As soon as the IN packet is received and written to the receive FIFO, the host generates an RXFLVL interrupt. 6. In response to the RXFLVL interrupt, read the received packet status to determine the number of bytes received, then read the receive FIFO accordingly.
Page 275 ...the world's most energy friendly microcontrollers if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 Frame) else if (ACK) Reset Error Count Mask ACK The application is expected to write the requests for the same channel when the Request queue space is available up to the count specified in the MC field before switching to another channel (if any).
Page 276: Normal Interrupt Out/In Transactions In Dma Mode
...the world's most energy friendly microcontrollers Figure 15.16. Normal Interrupt OUT/IN Transactions in DMA Mode Application Host Device init_reg( ch_1) Periodic Request init_reg( ch_2) Queue Assum e that this queue can hold 4 entries . ch_1 ch_2 fram e CHHLTD interrupt init_reg( ch_1) ch_1 CHHLTD interrupt...
Page 277 ...the world's most energy friendly microcontrollers Re-initialize Channel (in next b_interval - 1 Frame) else if (STALL) Transfer Done = 1 Reset Error Count Mask ACK De-allocate Channel else if (NAK or FRMOVRUN) Mask ACK Rewind Buffer Pointers Re-initialize Channel (in next b_interval - 1 Frame) if (NAK) Reset Error Count else if (XACTERR)
Page 278 ...the world's most energy friendly microcontrollers 1. Initialize and enable channel 2 as explained in Channel Initialization (p. 256) . 2. The host writes an IN request to the Request queue as soon as the channel 2 gets the grant from the arbiter (round-robin with fairness).
Page 279 ...the world's most energy friendly microcontrollers As soon as the channel is enabled, the core attempts to write the requests into the Request queue when the space is available up to the count specified in the MC field. 15.4.3.6.13 Isochronous OUT Transactions in Slave Mode To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p.
Page 280: Normal Isochronous Out/In Transactions In Slave Mode
...the world's most energy friendly microcontrollers Figure 15.17. Normal Isochronous OUT/IN Transactions in Slave Mode Application Host Device init_reg(ch_1) Periodic Requests init_reg( ch_2) Queue write _tx_fifo Asum e that this queue ( ch_1) can hold 4 entries. set_ch_en ch_1 ( ch_2) ch_2 fram e XFERCOMPL interrupt...
Page 281 ...the world's most energy friendly microcontrollers 15.4.3.6.14 Isochronous IN Transactions in Slave Mode To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 250) . Before it can communicate with the connected device, it must initialize a channel as described in Channel Initialization (p.
Page 282 ...the world's most energy friendly microcontrollers Reset Error Count De-allocate Channel else Unmask CHHLTD Disable Channel else if (XACTERR or BBLERR) Increment Error Count Unmask CHHLTD Disable Channel else if (CHHLTD) Mask CHHLTD if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel...
Page 283: Normal Isochronous Out/In Transactions In Dma Mode
...the world's most energy friendly microcontrollers Figure 15.18. Normal Isochronous OUT/IN Transactions in DMA Mode Application Host Device init_reg(ch_1) Periodic Request init_reg( ch_2) Queue Assum e that this queue can hold 4 entries . ch_1 ch_2 fram e CHHLTD interrupt init_reg(ch_1) ch_1 CHHLTD interrupt...
Page 284 ...the world's most energy friendly microcontrollers A typical isochronous IN operation in DMA mode is shown in Figure 15.18 (p. 283) . See channel 2 (ch_2). The assumptions are: • The application is attempting to receive one packet in every frame (up to 1 maximum packet size of 1,024 bytes).
Page 285 ...the world's most energy friendly microcontrollers 15.4.4 Device Programming Model Before you program the Device, be sure to read Overview: Programming the Core (p. 250) and Modes of operation (p. 253) 15.4.4.1 Endpoint Initialization This section addresses the following topics: •...
Page 286 ...the world's most energy friendly microcontrollers At this point, the device is ready to receive SOF packets and is configured to perform control transfers on control endpoint 0. 15.4.4.1.3 Initialization on SetAddress Command This section describes what the application must do when it receives a SetAddress command in a SETUP packet.
Page 287 ...the world's most energy friendly microcontrollers 15.4.4.1.7 Device DMA/Slave Mode Initialization The application must meed the following conditions to set up the device core to handle traffic. • In Slave mode, USB_GINTMSK.NPTXFEMPMSK, and USB_GINTMSK.RXFLVLMSK must be unset. • In DMA mode, the aforementioned interrupts must be masked. 15.4.4.1.8 Transfer Stop Process When the core is operating as a device, use the following programing sequence if you want to stop any transfers (because of an interrupt from the host, typically a reset).
Page 288 ...the world's most energy friendly microcontrollers Table 15.2. Device Mode SETUP Control Slave Generic Non-Periodic OUT Data Transfers Generic Non-Isochronous (Bulk and Control) IN in Slave and DMA OUT Data Transfers Data Transfers Without Modes (p. 289) Without Thresholding Thresholding in DMA and in DMA and Slave Slave Mode (p.
Page 289 ...the world's most energy friendly microcontrollers in DMA and Slave Modes (p. 305) Generic Periodic Control Read Transfers IN (Interrupt and (SETUP, Data IN, Status Isochronous) Data OUT) (p. 292) and Transfers Without Incomplete Isochronous Thresholding (p. 317) OUT Data Transfers and Generic Periodic IN in DMA and Slave Data Transfers Without...
Page 290 ...the world's most energy friendly microcontrollers 1. When a SETUP packet is received, the core writes the received data to the receive FIFO, without checking for available space in the receive FIFO and irrespective of the endpoint’s NAK and Stall bit settings.
Page 291 ...the world's most energy friendly microcontrollers Figure 15.19 (p. 291) charts this flow. Figure 15.19. Processing a SETUP Packet Wait for USB_DOEPx _INT.SETUP Back2Back Setup Interrupt bit set ? rem _supcnt = Setup_addr = Rd_Reg(USB_DOEPx _TSIZ) Rd_Reg(USB_DOEPx _DMA setup_cm d[31:0] = m em [4- 2 * rem _supcnt] setup_cm d[31:0] = m em [setup_addr- 8] setup_cm d[63:32] = m em [5- 2 * rem _supcnt] setup_cm d[63:32] = m em [setup_addr- 4]...
Page 292 ...the world's most energy friendly microcontrollers 15.4.4.2.2.1 Control Write Transfers (SETUP, Data OUT, Status IN) This section describes control write transfers. Application Programming Sequence 1. Assertion of the USB_DOEPx_INT.SETUP Packet interrupt indicates that a valid SETUP packet has been transferred to the application. See OUT Data Transfers in Slave and DMA Modes (p. 289) for more details.
Page 293: Two-Stage Control Transfer
...the world's most energy friendly microcontrollers 6. To perform a data OUT transfer in the status OUT phase, the application must program the core as described in OUT Data Transfers in Slave and DMA Modes (p. 289) . • The application must program the USB_DCFG.NZSTSOUTHSHK handshake field to a proper setting before transmitting an data OUT transfer for the Status stage.
Page 294: Host
...the world's most energy friendly microcontrollers • USB_DIEPx_CTL.CNAK = 1 7. When the application clears the IN NAK bit, the core interrupts the application with a USB_DIEPx_INT.INTKNTXFEMP. On this interrupt, the application enables the control IN endpoint with a USB_DIEPx_TSIZ.XFERSIZE of 0 and a USB_DIEPx_TSIZ.PKTCNT of 1. This results in a zero-length data packet for the status IN token on the USB.
Page 295 ...the world's most energy friendly microcontrollers a. SETUP Packet Pattern: PKTSTS = SETUP, BCNT = 0x008, EPNUM = Control EP Num, DPID = D0. This data indicates that a SETUP packet for the specified endpoint is now available for reading from the receive FIFO. b.
Page 296 ...the world's most energy friendly microcontrollers 4. Once the application detects this interrupt, it can assume that the core is in Global OUT NAK mode. The application can clear this interrupt by clearing the USB_DCTL.SGOUTNAK bit. Application Programming Sequence 1. To stop receiving any kind of data in the receive FIFO, the application must set the Global OUT NAK bit by programming the following field.
Page 297 ...the world's most energy friendly microcontrollers 4. If the application is setting or clearing a STALL for an endpoint due to a SetFeature.Endpoint Halt or ClearFeature.Endpoint Halt command, the Stall bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint.
Page 298: Slave Mode Bulk Out Transaction
...the world's most energy friendly microcontrollers • In all the above three cases, the packet count is not decremented because no data is written to the receive FIFO. 3. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set.
Page 299 ...the world's most energy friendly microcontrollers Figure 15.22. Slave Mode Bulk OUT Transaction Applicatio Host Device init_ out_ ep XFERSIZE = 512 bytes PKTCNT= 1 wr_reg(USB_DOEPx _TSIZ) EPENA = 1 CNAK = 1 wr_reg(USB_DOEPx _CTL) 512 bytes x act_1 RXFLVL INTR idle until intr rcv_out_pkt()
Page 300 ...the world's most energy friendly microcontrollers 3. In Slave mode, when isochronous OUT endpoints are supported in the device, the application must read all isochronous OUT data packets from the receive FIFO (data and status) before the end of the periodic frame (USB_GINTSTS.EOPF interrupt). In DMA mode, the application must guarantee enough bandwidth to allow emptying the isochronous OUT data packet from the receive FIFO before the end of each periodic frame.
Page 301 ...the world's most energy friendly microcontrollers 15.4.4.2.2.10 Generic Interrupt OUT Data Transfers Using Periodic Transfer Interrupt Feature This section describes a regular INTR OUT data transfer with the Periodic Transfer Interrupt feature. To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p.
Page 302 ...the world's most energy friendly microcontrollers • If there is no space in the receive FIFO, interrupt data packets are ignored and not written to the receive FIFO. Additionally, interrupt OUT tokens receive a NAK handshake reply. 2. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set.
Page 303 ...the world's most energy friendly microcontrollers • Number of USB packets in which this payload was received = application-programmed initial packet count – core updated final packet count. • If for some reason, the host stop sending tokens, there will be no interrupt to the application, and the application must timeout on its own.
Page 304 ...the world's most energy friendly microcontrollers Figure 15.23. ISOC OUT Application Flow for Periodic Transfer Interrupt Feature Note: 1 . The ( micro -) frame number and PID field are not updated for Periodic OUT packets 2 . In Periodic OUT transfers any short packet results in an XferComplete Interrupt and disables the endpoint The application must reenable the...
Page 305: Isochronous Out Core Internal Flow For Periodic Transfer Interrupt Feature
...the world's most energy friendly microcontrollers • The last OUT data packet written to the receive FIFO is a short packet (0 < packet size < maximum packet size). 8. When the DMA pops this entry (OUT Data Transfer Completed), a Transfer Completed interrupt is generated for the endpoint or the endpoint enable is cleared.
Page 306: Bulk In Stall
...the world's most energy friendly microcontrollers 2. When the core detects an end of periodic frame before transfer completion to all isochronous OUT endpoints, it asserts the USB_GINTSTS.INCOMPLP (Incomplete Isochronous OUT data) interrupt, indicating that a USB_DOEPx_INT.XFERCOMPL interrupt is not asserted on at least one of the isochronous OUT endpoints.
Page 307 ...the world's most energy friendly microcontrollers 15.4.4.2.3.1 Packet Write in Slave Mode This section describes how the application writes data packets to the endpoint FIFO in Slave mode. 1. The application can either choose polling or interrupt mode. • In polling mode, application monitors the status of the endpoint transmit data FIFO, by reading the USB_DIEPx_TXFSTS register, to determine, if there is enough space in the data FIFO.
Page 308 ...the world's most energy friendly microcontrollers 1. When the application sets the IN NAK for a particular endpoint, the core stops transmitting data on the endpoint, irrespective of data availability in the endpoint’s transmit FIFO. 2. Non-isochronous IN tokens receive a NAK handshake reply •...
Page 309 ...the world's most energy friendly microcontrollers The application must poll the USB_GRSTCTL register, until the TXFFLSH bit is cleared by the core, which indicates the end of flush operation. To transmit new data on this endpoint, the application can re-enable the endpoint at a later point. 15.4.4.2.3.5 Bulk IN Stall These notes refer to Figure 15.25 (p.
Page 310 ...the world's most energy friendly microcontrollers a. The core receives a corrupted isochronous IN token on at least one isochronous IN endpoint. In this case, the application detects a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt. b. The application or DMA is slow to write the complete data payload to the transmit FIFO and an IN token is received before the complete data payload is written to the FIFO.
Page 311 ...the world's most energy friendly microcontrollers 6. If the application sets or clears a STALL for an endpoint due to a SetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, the Stall bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint. Special Case: Stalling the Control IN/OUT Endpoint The core must stall IN/OUT tokens if, during the Data stage of a control transfer, the host sends more IN/OUT tokens than are specified in the SETUP packet.
Page 312 ...the world's most energy friendly microcontrollers Figure 15.26. USBTRDTIM Max Timing Case ERROR wrong image Host Device Application XferSize = 1025 bytes PktCnt = 3 EPEna = 1 idle( wait_intr) setup_ np_in_ pkt x act_ 1 data rdy do_in_ x fer x act _ 1 of 2 setup_ np_in_ pkt 512 bytes...
Page 313 ...the world's most energy friendly microcontrollers • To transmit a few maximum-packet-size packets and a short packet at the end of the transfer: • Transfer size[epnum] = n * mps[epnum] + sp (where n is an integer >= 0, and 0 <= sp < mps[epnum]) •...
Page 314: Slave Mode Bulk In Transaction
...the world's most energy friendly microcontrollers Application Programming Sequence 1. Program the USB_DIEPx_TSIZ register with the transfer size and corresponding packet count. In DMA mode, also program the USB_DIEPx_DMAADDR register. 2. Program the USB_DIEPx_CTL register with the endpoint characteristics and set the CNAK and Endpoint Enable bits.
Page 315: Slave Mode Bulk In Transfer (Pipelined Transaction)
...the world's most energy friendly microcontrollers Slave Mode Bulk IN Transfer (Pipelined Transaction) These notes refer to Figure 15.28 (p. 316) 1. The host attempts to read data (IN token) from an endpoint. 2. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO.
Page 316: Slave Mode Bulk In Two-Endpoint Transfer
...the world's most energy friendly microcontrollers Figure 15.28. Slave Mode Bulk IN Transfer (Pipelined Transaction) Host Device Application x fer_ cnt = 1025 bytes pkt_ cnt = 3 INTKNTXFEMP idle until intr INTR EP Enable = 1 wr_reg(x fer_ size_reg) x act_ 1 setup_ np_in_pkt x act _...
Page 317 ...the world's most energy friendly microcontrollers 13. M eanwhile, the application has initialized the data for the next two packets in the TxFIFO (ep2.xact2 and ep1.xact3, in order). The application has finished initializing data for the two endpoints involved in this scenario. 14.
Page 318 ...the world's most energy friendly microcontrollers as described in Endpoint Initialization (p. 285) . For packet writes in Slave mode, see: Packet Write in Slave Mode (p. 307) . Application Requirements 1. Application requirements 1, 2, 3, and 4 of Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p.
Page 319 ...the world's most energy friendly microcontrollers 2. In Slave mode, the application must also write the required data to the associated transmit FIFO for the endpoint. In DMA mode, the core fetches the data for the endpoint from memory, according to the application setting.
Page 320 ...the world's most energy friendly microcontrollers 1. Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer is part of a single buffer, and must program the size of that buffer and its start address (in DMA mode) to the endpoint-specific registers.
Page 321 ...the world's most energy friendly microcontrollers 6. For Periodic IN endpoints, the data must always be prefetched 1 frame ahead for transmission in the next frame. This can be done, by enabling the Periodic IN endpoint 1 frame ahead of the frame in which the data transfer is scheduled.
Page 322 ...the world's most energy friendly microcontrollers 3. Every time either the core’s internal DMA writes a packet to the transmit FIFO, the transfer size for that endpoint is decremented by the packet size. The data is fetched from DMA or application memory until the transfer size for the endpoint becomes 0.
Page 323 ...the world's most energy friendly microcontrollers Figure 15.31. Periodic IN Core Internal Flow for Periodic Transfer Interrupt Feature START NOTE Core will fetch data only from DWORD Aligned addresses Core will not tag Periodic IN Packets to a specific ( micro ) frame number In case core is not able to send out data for the current ( micro ) frame the If (USB_DIEPx _CTL.CNAK = 0b1) &&...
Page 324 ...the world's most energy friendly microcontrollers 6. The application must service the Session Request Detected interrupt and turn on the Port Power bit by writing the Port Power bit in the Host Port Control and Status register. The PHY indicates port power-on by detecting a valid VBUS level.
Page 325 ...the world's most energy friendly microcontrollers The application must read the Current Mode bit in the OTG Control and Status register to determine Device mode operation. 4. The B-device detects the connection, issues a USB reset, and enumerates the core for data traffic. 5.
Page 326 ...the world's most energy friendly microcontrollers 15.4.6 OTG Revision 2.0 Programming Model OTG Revision 2.0 supports the new Attach Detection Protocol (ADP). This protocol enables a local device (an OTG device or Embedded Host) to detect when a remote device is attached or detached. Note ADP is not supported by the core.
Page 327 ...the world's most energy friendly microcontrollers Figure 15.32. SRP Detection by Core When Operating as A-device Host m ode (PHY not driving VBUS) Program USB_GINTMSK. (Unm ask OTGINT, MODEMIS, SESSREQINT) If host’s application decides to Interrupt? turn on VBUS voluntarily, then the application need not wait for SRP from device...
Page 328 ...the world's most energy friendly microcontrollers Figure 15.33. SRP Initiation by the Core When Acting as a B-Device Device (OTG FSM in b_idle state) 1. Program USB_GINTMSK (unm ask OTGINT) 2. Read USB_GOTGCTL Yes ( This indicates that VBUS is already being driven and hence there is no need for a SRP ) USB_GOTGCTL.
Page 329: Hnp When The Core Is An A-Device
...the world's most energy friendly microcontrollers Figure 15.34. HNP When the Core is an A-Device Host to Device to Host Host m ode 1. Unm ask (Send SetFeature Com m and to enable USB_GINTSTS.ERLYSUSP b_hnp_enable feature in HNP capable 2. Device Initialization Steps devices.
Page 330: Hnp When The Core Is A B-Device
...the world's most energy friendly microcontrollers Figure 15.35. HNP When the Core is a B-Device Read USB_GOTGINT USB_GOTGINT. HSTNEGSUCSTSCHNG = 1 ? Device m ode (Receive SetFeature Com m and and OTG FSM is in b_peripheral state) Clear USB_GOTGINT. HSTNEGSUCSTSCHNG 1.
Page 331 ...the world's most energy friendly microcontrollers register) within 150 ms (TB_ACON_BSE0) of getting a USB_HPRT.PRTCONNDET interrupt. 15.4.7 FIFO RAM Allocation 15.4.7.1 Data FIFO RAM Allocation External RAM must be allocated among different FIFOs in the core before any transactions can start. The application must follow this procedure every time it changes core FIFO RAM allocation.
Page 332 ...the world's most energy friendly microcontrollers Packet Size / 4) + 1 spaces must be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to AHB, the USB can receive the subsequent packet.
Page 333 ...the world's most energy friendly microcontrollers The application must wait until the TXFFLSH bit and the RXFFLSH bits are cleared before performing any operation on the core. 15.4.7.1.2 Host Mode Considerations for allocating data RAM for Host Mode FIFOs are listed here: Receive FIFO RAM allocation: Status information is written to the FIFO along with each received packet.
Page 334 ...the world's most energy friendly microcontrollers 2. Non-periodic Transmit FIFO Size Register (USB_GNPTXFSIZ) • USB_GNPTXFSIZ.NPTXFDEP = tx_fifo_size[0]; • USB_GNPTXFSIZ.NPTXFSTADDR = rx_fifo_size; 3. Host Periodic Transmit FIFO Size Register (USB_HPTXFSIZ) • USB_HPTXFSIZ.PTXFSIZE = tx_fifo_size[1]; • USB_HPTXFSIZ.PTXFSTADDR = USB_GNPTXFSIZ.NPTXFSTADDR + tx_fifo_size[0]; 4. The transmit FIFOs and receive FIFO must be flushed after RAM allocation for proper FIFO function. •...
Page 335 ...the world's most energy friendly microcontrollers • Slave mode Minimum requirement: (largest USB packet used / 4) + 1 for status information + 1 transfer complete • DMA mode (largest USB packet used / 4) + 1 for status information + 1 transfer complete + 1 location each bulk/ control out endpoint for handling NAK scenario Host Non-Periodic TxFIFO = •...
Page 336 ...the world's most energy friendly microcontrollers ((Host Non-Periodic TxFIFO + Host peiodic TxFIFO) or (Device IN Endpoint TxFIFO #0 + #1 + #2 + #n)); choose the largest one + (1 location per Host channel or 1 location per Device Endpoint direction; choose the largest one) //Slave mode OTG Total RAM = (Device RxFIFO or Host RxFIFO;...
Page 337 ...the world's most energy friendly microcontrollers the largest one) //Slave mode OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) + ((Host Non-Periodic TxFIFO + Host periodic TxFIFO) OR (Device IN Endpoint TxFIFO #0 + #1 + #2 + #n); choose the largest one) 15.4.7.2 Dynamic FIFO Allocation The application can change the RAM allocation for each FIFO during the operation of the core.
Page 338 ...the world's most energy friendly microcontrollers 4. Check that USB_GRSTCTL.TXFFLSH =0. If it is 0, then write the TxFIFO number you want to flush to USB_GRSTCTL.TXFNUM. 5. Set USB_GRSTCTL.TXFFLSH=1and wait for it to clear. 6. Set the USB_DCTL.GCNPINNAK bit. 15.4.7.2.4 Flushing RxFIFOs in the Core The application can flush all RxFIFOs in the core using USB_GRSTCTL.RXFFLSH as follows: 1.
Page 339 ...the world's most energy friendly microcontrollers 15.4.8 Suspend/Resume and SRP This chapter describes different methods of saving power when the USB is suspended. This chapter discusses the following topics: • Placing PHY in Low Power Mode Without Entering Suspend (p. 339) •...
Page 340 ...the world's most energy friendly microcontrollers • USB_HPRT.PRTPWR = 1 • USB_HPRT.PRTENA = 0 3. Wait for the USB_HPRT Port Connect Detected (PRTCONNDET) bit to be set and do the enumeration of Device. 15.4.8.1.2 When the Core is in Device Mode To make PHY enter low power mode, complete the following steps: 1.
Page 341 ...the world's most energy friendly microcontrollers 3. The application sets the Power Clamp bit in the Power and Clock Gating Control register. 4. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register. 5.
Page 342 ...the world's most energy friendly microcontrollers • USB_GAHBCFG • USB_DIEPMSK • USB_GUSBCFG • USB_DOEPMSK • USB_GRXFSIZ • USB_DIEPx_CTL • USB_GNPTXFSIZ • USB_DIEPx_TSIZ • USB_DCFG • USB_DIEPx_DMAADDR • USB_PCGCCTL • USB_DIEPTXFn 2. The application sets the Port Suspend bit in the Host Port CSR and the core drives a USB suspend. 3.
Page 343 ...the world's most energy friendly microcontrollers 6. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. 7. Enter EM2. Host Mode Sessions Start (SRP) (EM2 -> EM0) Sequence of operations: 1. The core detects SRP (data line pulsing) on the bus. The core de-asserts the suspend_n signal to the PHY, generating the PHY clock.
Page 344 ...the world's most energy friendly microcontrollers 5. The application sets the USB_PCGCCTL.STOPPCLK bit. 6. Switch USB Core Clock (USBC) to 32 kHz. 7. Enter EM2. Device Mode Resume (EM2 -> EM0) Sequence if operations: 1. The core detects Resume signaling on the USB. The core generates a Resume Detected interrupt. 2.
Page 345 ...the world's most energy friendly microcontrollers 9. Wait for remote wakeup time (1-15ms) and then program USB_DCTL by performing read-modify- write to set USB_DCTL.RMTWKUPSIG = 0. Device Mode Session End (EM0 -> EM2) Sequence of operations: 1. The core detects a USB suspend and generates a Suspend Detected interrupt. The host turns off VBUS.
Page 346 ...the world's most energy friendly microcontrollers 1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend. 2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk internally.
Page 347 ...the world's most energy friendly microcontrollers 3. The core remains in Suspend mode. 4. The Resume signaling from the host is detected. A Resume Detected interrupt is generated. 5. The application clears the Gate hclk bit and the Stop PHY Clock bit. 6.
Page 348 ...the world's most energy friendly microcontrollers Host, the application must not access registers from the other mode. If an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the Core Interrupt register (USB_GINTSTS.MODEMIS). When the core switches from one mode to another, the registers in the new mode must be reprogrammed as they would be after a power-on reset.
Page 349: Register Map
...the world's most energy friendly microcontrollers 15.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 USB_CTRL System Control Register 0x004 USB_STATUS System Status Register 0x008 USB_IF Interrupt Flag Register 0x00C USB_IFS Interrupt Flag Set Register 0x010...
Page 350 ...the world's most energy friendly microcontrollers Offset Name Type Description USB_HCx_INT RW1H Host Channel x Interrupt Register USB_HCx_INTMSK Host Channel x Interrupt Mask Register USB_HCx_TSIZ Host Channel x Transfer Size Register USB_HCx_DMAADDR Host Channel x DMA Address Register 0x3C6A0 USB_HC13_CHAR Host Channel x Characteristics Register 0x3C6A8 USB_HC13_INT...
Page 351 ...the world's most energy friendly microcontrollers Offset Name Type Description 0x3C994 USB_DIEP3_DMAADDR Device IN Endpoint x+1 DMA Address Register 0x3C998 USB_DIEP3_TXFSTS Device IN Endpoint x+1 Transmit FIFO Status Register 0x3C9A0 USB_DIEP4_CTL Device IN Endpoint x+1 Control Register 0x3C9A8 USB_DIEP4_INT Device IN Endpoint x+1 Interrupt Register 0x3C9B0 USB_DIEP4_TSIZ Device IN Endpoint x+1 Transfer Size Register...
Page 352 ...the world's most energy friendly microcontrollers Offset Name Type Description USB_FIFO0Dx Device EP 0/Host Channel 0 FIFO 0x3D7FC USB_FIFO0D511 Device EP 0/Host Channel 0 FIFO 0x3E000 USB_FIFO1D0 Device EP 1/Host Channel 1 FIFO USB_FIFO1Dx Device EP 1/Host Channel 1 FIFO 0x3E7FC USB_FIFO1D511 Device EP 1/Host Channel 1 FIFO...
Page 353: Register Description
...the world's most energy friendly microcontrollers Offset Name Type Description USB_FIFORAMx Direct Access to Data FIFO RAM for Debugging (2 KB) 0x5C7FC USB_FIFORAM511 Direct Access to Data FIFO RAM for Debugging (2 KB) 15.6 Register Description 15.6.1 USB_CTRL - System Control Register Offset Bit Position 0x000...
Page 354 ...the world's most energy friendly microcontrollers 15.6.2 USB_STATUS - System Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) VREGOS VREGO Sense Output USB_VREGO Voltage Sense output.
Page 355 ...the world's most energy friendly microcontrollers Name Reset Access Description VREGOSL Set VREGO Sense Low Interrupt Flag Write to 1 to set the VREGO Sense Low Interrupt Flag. VREGOSH Set VREGO Sense High Interrupt Flag Write to 1 to set the VREGO Sense High Interrupt Flag. 15.6.5 USB_IFC - Interrupt Flag Clear Register Offset Bit Position...
Page 356 ...the world's most energy friendly microcontrollers 15.6.7 USB_ROUTE - I/O Routing Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DMPUPEN DMPU Pin Enable When set, the USB_DMPU pin is enabled.
Page 357 ...the world's most energy friendly microcontrollers Name Reset Access Description DBNCTIME Long/Short Debounce Time host only Indicates the debounce time of a detected connection. Value Mode Description LONG Long debounce time, used for physical connections (100 ms + 2.5 us). SHORT Short debounce time, used for soft connections (2.5 us).
Page 358 ...the world's most energy friendly microcontrollers Offset Bit Position 0x3C004 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DBNCEDONE RW1H Debounce Done host only The core sets this bit when the debounce is completed after the device connect.
Page 359 ...the world's most energy friendly microcontrollers Offset Bit Position 0x3C008 Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) NOTIALLDMAWRIT Notify All DMA Writes This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to the Channel/ Endpoint.
Page 360 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description SINGLE Single transfer. INCR Incrementing burst of unspecified length. INCR4 4-beat incrementing burst. INCR8 8-beat incrementing burst. INCR16 16-beat incrementing burst. GLBLINTRMSK Global Interrupt Mask host and device The application uses this bit to mask or unmask the interrupt line assertion to itself.
Page 361 ...the world's most energy friendly microcontrollers Name Reset Access Description HNPCAP HNP-Capable host and device The application uses this bit to control the core's HNP capabilities. Set to enable HNP capability. SRPCAP SRP-Capable host and device The application uses this bit to control the core's SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to activate VBUS and start a session.
Page 362 ...the world's most energy friendly microcontrollers Name Reset Access Description Interrupt ensures the core is not reading from the FIFO. USB_GRSTCTL.AHBIDLE ensures the core is not writing anything to the FIFO. Flushing is normally recommended when FIFOs are reconfigured. FIFO flushing is also recommended during device endpoint disable.
Page 363 ...the world's most energy friendly microcontrollers Name Reset Access Description In Host mode, this interrupt is asserted when a session request is detected from the device. In Device mode, this interrupt is asserted when the VBUS voltage reaches the session-valid level. This bit can be set only by the core and the application should write 1 to clear. DISCONNINT RW1H Disconnect Detected Interrupt host only...
Page 364 ...the world's most energy friendly microcontrollers Name Reset Access Description Indicates that the period specified in the Periodic Frame Interval field of the Device Configuration register (DCFG_PERFRINT) has been reached in the current microframe. ISOOUTDROP RW1H Isochronous OUT Packet Dropped Interrupt device only The core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum packet size packet for the isochronous OUT endpoint.
Page 365 ...the world's most energy friendly microcontrollers 15.6.14 USB_GINTMSK - Interrupt Mask Register This register works with the Interrupt Register (USB_GINTSTS) to interrupt the application. When an interrupt bit is masked (bit is 0), the interrupt associated with that bit is not generated. However, the USB_GINTSTS register bit corresponding to that interrupt is still set.
Page 366 ...the world's most energy friendly microcontrollers Name Reset Access Description EOPFMSK End of Periodic Frame Interrupt Mask device only Set to 1 to unmask EOPF interrupt. ISOOUTDROPMSK Isochronous OUT Packet Dropped Interrupt Mask device only Set to 1 to unmask ISOOUTDROP interrupt. ENUMDONEMSK Enumeration Done Mask device only Set to 1 to unmask ENUMDONE interrupt.
Page 367 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 24:21 Frame Number device only This is the least significant 4 bits of the Frame number in which the packet is received on the USB. 20:17 PKTSTS Packet Status (host or device)
Page 368 ...the world's most energy friendly microcontrollers Name Reset Access Description 24:21 Frame Number device only This is the least significant 4 bits of the Frame number in which the packet is received on the USB. 20:17 PKTSTS Packet Status (host or device) Indicates the status of the received packet.
Page 369 ...the world's most energy friendly microcontrollers 15.6.18 USB_GNPTXFSIZ - Non-periodic Transmit FIFO Size Register The application can program the RAM size and the memory start address for the Non-periodic TxFIFO. Offset Bit Position 0x3C028 Reset Access Name Name Reset Access Description 31:16 NPTXFINEPTXF0DEP...
Page 370 ...the world's most energy friendly microcontrollers Name Reset Access Description Bit [0]: Terminate (last Entry for selected channel/endpoint). 23:16 NPTXQSPCAVAIL 0x08 Non-periodic Transmit Request Queue Space Available Indicates the amount of free space (locations) available in the Non-periodic Transmit Request Queue. This queue holds both IN and OUT requests in Host mode.
Page 371 ...the world's most energy friendly microcontrollers Name Reset Access Description This field contains the memory start address for Host Periodic TxFIFO. 15.6.22 USB_DIEPTXF1 - Device IN Endpoint Transmit FIFO 1 Size Register This register holds the size and memory start address of IN endpoint TxFIFO 1 in Device mode. For IN endpoint FIFO 0 use USB_GNPTXFSIZ register for programming the size and memory start address.
Page 372 ...the world's most energy friendly microcontrollers Name Reset Access Description 10:0 INEPNTXFSTADDR 0x600 IN Endpoint FIFO 2 Transmit RAM Start Address This field contains the memory start address for IN endpoint Transmit FIFO 2. 15.6.24 USB_DIEPTXF3 - Device IN Endpoint Transmit FIFO 3 Size Register This register holds the size and memory start address of IN endpoint TxFIFO 3 in Device mode.
Page 373 ...the world's most energy friendly microcontrollers Name Reset Access Description 15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 INEPNTXFSTADDR 0xA00 IN Endpoint FIFO 4 Transmit RAM Start Address This field contains the memory start address for IN endpoint Transmit FIFO 4.
Page 374 ...the world's most energy friendly microcontrollers Name Reset Access Description This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512. 15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 INEPNTXFSTADDR 0xE00...
Page 375 ...the world's most energy friendly microcontrollers Offset Bit Position 0x3C404 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) HFIRRLDCTRL Reload Control This bit allows dynamic reloading of the HFIR register during run time.
Page 376 ...the world's most energy friendly microcontrollers 15.6.31 USB_HPTXSTS - Host Periodic Transmit FIFO/Queue Status Register This read-only register contains the free space information for the Periodic TxFIFO and the Periodic Transmit Request Queue. Offset Bit Position 0x3C410 Reset Access Name Name Reset Access...
Page 377 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 13:0 HAINT 0x0000 Channel Interrupt for channel 0 - 13. When the interrupt bit for a channel x set, one or more of the interrupt flags in the USB_HCx_INT are set.
Page 378 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description High speed. Full speed. Low speed. 16:13 PRTTSTCTL Port Test Control The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port.
Page 379 ...the world's most energy friendly microcontrollers Name Reset Access Description The core sets this bit when a device connection is detected to trigger an interrupt to the application using the Host Port Interrupt bit of the Core Interrupt register (USB_GINTSTS.PRTINT). This bit can be set only by the core and the application should write 1 to clear it.
Page 380 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description Direction is IN. 14:11 EPNUM Endpoint Number Indicates the endpoint number on the device serving as the data source or sink. 10:0 0x000 Maximum Packet Size Indicates the maximum packet size of the associated endpoint. 15.6.36 USB_HCx_INT - Host Channel x Interrupt Register This register indicates the status of a channel with respect to USB- and AHB-related events.
Page 381 ...the world's most energy friendly microcontrollers Name Reset Access Description CHHLTD RW1H Channel Halted In DMA mode this bit indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer. XFERCOMPL RW1H Transfer Completed...
Page 382 ...the world's most energy friendly microcontrollers 15.6.38 USB_HCx_TSIZ - Host Channel x Transfer Size Register Offset Bit Position 0x3C510 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:29 Packet ID The application programs this field with the packet ID type to use for the initial transaction.
Page 383 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 DMAADDR 0xXXXXXXXX DMA Address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored.
Page 384 ...the world's most energy friendly microcontrollers 15.6.41 USB_DCTL - Device Control Register Offset Bit Position 0x3C804 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) NAKONBBLE NAK on Babble Error Set NAK automatically on babble.
Page 385 ...the world's most energy friendly microcontrollers Name Reset Access Description The application uses this bit to signal the core to do a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB.
Page 386 ...the world's most energy friendly microcontrollers status in the USB_DIEP0INT/USB_DIEPx_INT register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. Offset Bit Position 0x3C810 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 387 ...the world's most energy friendly microcontrollers Offset Bit Position 0x3C814 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) NAKMSK NAK interrupt Mask Set to 1 to unmask NAK Interrupt.
Page 388 ...the world's most energy friendly microcontrollers Offset Bit Position 0x3C818 Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) OUTEPINT6 OUT Endpoint 6 Interrupt Bit This bit is set when on or more of the interrupt flags in USB_DOEP5_INT are set.
Page 389 ...the world's most energy friendly microcontrollers Offset Bit Position 0x3C81C Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) OUTEPMSK6 OUT Endpoint 6 Interrupt mask Bit Set to 1 to unmask USB_DAINT.OUTEPINT6.
Page 390 ...the world's most energy friendly microcontrollers Offset Bit Position 0x3C828 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DVBUSDIS 0x17D7 Device VBUS Discharge Time Specifies the VBUS discharge time after VBUS pulsing during SRP.
Page 391 ...the world's most energy friendly microcontrollers Offset Bit Position 0x3C834 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DIEPEMPMSK 0x0000 IN EP Tx FIFO Empty Interrupt Mask Bits These bits acts as mask bits for USB_DIEP0INT.TXFEMP/USB_DIEPx_INT.TXFEMP interrupt.
Page 392 ...the world's most energy friendly microcontrollers Name Reset Access Description The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Nonperiodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 393 ...the world's most energy friendly microcontrollers Name Reset Access Description PKTDRPSTS RW1H Packet Drop Status This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. 10:8 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 394 ...the world's most energy friendly microcontrollers Name Reset Access Description Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the TxFIFO.
Page 395 ...the world's most energy friendly microcontrollers 15.6.55 USB_DIEPx_CTL - Device IN Endpoint x+1 Control Register The application uses this register to control the behavior of each logical endpoint other than endpoint 0. Offset Bit Position 0x3C920 Reset Access Name Name Reset Access Description...
Page 396 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description Isochronous Endpoint. BULK Bulk Endpoint. Interrupt Endpoint. NAKSTS NAK Status When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is transmitting NAK handshakes on this endpoint.
Page 397 ...the world's most energy friendly microcontrollers Name Reset Access Description BBLEERR RW1H NAK Interrupt The core generates this interrupt when babble is received for the endpoint. PKTDRPSTS RW1H Packet Drop Status This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.
Page 398 ...the world's most energy friendly microcontrollers Name Reset Access Description 30:29 Multi Count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 28:19 PKTCNT 0x000...
Page 399 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 SPCAVAIL 0x0200 TxFIFO Space Available Indicates the amount of free space available in the Endpoint TxFIFO. Values are in terms of 32-bit words. 15.6.60 USB_DOEP0CTL - Device OUT Endpoint 0 Control Register The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
Page 400 ...the world's most energy friendly microcontrollers Name Reset Access Description 14:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Maximum Packet Size The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0. Value Mode Description...
Page 401 ...the world's most energy friendly microcontrollers Name Reset Access Description Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. AHBERR RW1H AHB Error...
Page 402 ...the world's most energy friendly microcontrollers 15.6.63 USB_DOEP0DMAADDR - Device OUT Endpoint 0 DMA Address Register Offset Bit Position 0x3CB14 Reset Access Name Name Reset Access Description 31:0 DOEP0DMAADDR 0xXXXXXXXX DMA Address Holds the start address of the external memory for storing endpoint data. For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets.
Page 403 ...the world's most energy friendly microcontrollers Name Reset Access Description For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register to DATA1ODD. For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA1ODD).
Page 404 ...the world's most energy friendly microcontrollers 15.6.65 USB_DOEPx_INT - Device OUT Endpoint x+1 Interrupt Register This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register when the OUT Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.OEPINT) is set.
Page 405 ...the world's most energy friendly microcontrollers 15.6.66 USB_DOEPx_TSIZ - Device OUT Endpoint x+1 Transfer Size Register The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint x+1 Control register (USB_DOEPx_CTL.EPENA), the core modifies this register.
Page 406 ...the world's most energy friendly microcontrollers 15.6.67 USB_DOEPx_DMAADDR - Device OUT Endpoint x+1 DMA Address Register Offset Bit Position 0x3CB34 Reset Access Name Name Reset Access Description 31:0 DMAADDR 0xXXXXXXXX DMA Address Holds the start address of the external memory for storing endpoint data. For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets.
Page 407 ...the world's most energy friendly microcontrollers Name Reset Access Description PWRCLMP Power Clamp The application sets this bit before the power is turned off to clamp the signals between the power-on modules and the power-off modules of the USB core. The application clears the bit to disable the clamping. GATEHCLK Gate HCLK The application sets this bit to gate the clock (HCLK) to modules other than the AHB Slave and Master and wakeup logic when the...
Page 408 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 FIFO1D 0xXXXXXXXX Device EP 1/Host Channel 1 FIFO FIFO 1 push/pop region. Used in slave mode. 15.6.71 USB_FIFO2Dx - Device EP 2/Host Channel 2 FIFO This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 2 or channel 2, in a given direction.
Page 409 ...the world's most energy friendly microcontrollers Name Reset Access Description FIFO 3 push/pop region. Used in slave mode. 15.6.73 USB_FIFO4Dx - Device EP 4/Host Channel 4 FIFO This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 4 or channel 4, in a given direction.
Page 410 ...the world's most energy friendly microcontrollers 15.6.75 USB_FIFO6Dx - Device EP 6/Host Channel 6 FIFO This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 6 or channel 6, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel.
Page 411 ...the world's most energy friendly microcontrollers Offset Bit Position 0x45000 Reset Access Name Name Reset Access Description 31:0 FIFO8D 0xXXXXXXXX Host Channel 8 FIFO FIFO 8 push/pop region. Used in slave mode. 15.6.78 USB_FIFO9Dx - Host Channel 9 FIFO This register, available in Host mode, is used to read or write the FIFO space for channel 9, in a given direction.
Page 412 ...the world's most energy friendly microcontrollers Offset Bit Position 0x47000 Reset Access Name Name Reset Access Description 31:0 FIFO10D 0xXXXXXXXX Host Channel 10 FIFO FIFO 10 push/pop region. Used in slave mode. 15.6.80 USB_FIFO11Dx - Host Channel 11 FIFO This register, available in Host mode, is used to read or write the FIFO space for channel 11, in a given direction.
Page 413 ...the world's most energy friendly microcontrollers Offset Bit Position 0x49000 Reset Access Name Name Reset Access Description 31:0 FIFO12D 0xXXXXXXXX Host Channel 12 FIFO FIFO 12 push/pop region. Used in slave mode. 15.6.82 USB_FIFO13Dx - Host Channel 13 FIFO This register, available in Host mode, is used to read or write the FIFO space for channel 13, in a given direction.
Page 414 ...the world's most energy friendly microcontrollers 15.6.83 USB_FIFORAMx - Direct Access to Data FIFO RAM for Debugging (2 KB) Offset Bit Position 0x5C000 Reset Access Name Name Reset Access Description 31:0 FIFORAM 0xXXXXXXXX FIFO RAM Direct Access to Data FIFO RAM for Debugging (2 KB) www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 415: C - Inter-Integrated Circuit Interface
...the world's most energy friendly microcontrollers 16 I C - Inter-Integrated Circuit Interface Quick Facts What? 0 1 2 3 The I C interface allows communication on I C-buses with the lowest energy consumption possible. Why? C m aster/ slave C is a popular serial bus that enables communication with a number of external devices using only two I/O pins.
Page 416: Functional Description
...the world's most energy friendly microcontrollers 16.3 Functional Description An overview of the I C module is shown in Figure 16.1 (p. 416) . Figure 16.1. I C Overview Peripheral Bus C Control and Transm it Buffer Receive Buffer Status I2Cn_SDA Sym bol Transm it...
Page 417: C Start And Stop Conditions
...the world's most energy friendly microcontrollers Note If V drops below the voltage on SCL and SDA lines, the MCU could become back powered and pull the SCL and SDA lines low. 16.3.1.1 START and STOP Conditions START and STOP conditions are used to initiate and stop transactions on the I C-bus.
Page 418 ...the world's most energy friendly microcontrollers on the bus can try to gain control of it. If the current master wishes to make another transfer immediately after the current, it can start a new transfer directly by transmitting a repeated START condition (Sr) instead of a STOP followed by a START.
Page 419 ...the world's most energy friendly microcontrollers 16.3.1.4 10-bit Addressing To address a slave using a 10-bit address, two bytes are required to specify the address instead of one. The seven first bits of the first byte must then be 1111 0XX, where XX are the two most significant bits of the 10-bit address.
Page 420: C High And Low Periods For Low Clkdiv
...the world's most energy friendly microcontrollers When enabling the I C, the ABORT command or the Bus Idle Timeout feature must be applied prior to use even if the BUSY flag is not set. 16.3.3 Safely Disabling and Changing Slave Configuration The I C slave is partially asynchronous, and some precautions are necessary to always ensure a safe slave disable or slave configuration change.
Page 421 ...the world's most energy friendly microcontrollers Table 16.3. I C Clock Mode HFPERCLK Clock Low High Sm max frequency Fm max frequency Fm+ max frequency frequency (MHz) Ratio (CLHR) (kHz) (kHz) (kHz) 1000 1000 1000 1000 1000 16.3.5 Arbitration Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When arbitration is enabled, the value on SDA is sensed every time the I C module attempts to change its value.
Page 422 ...the world's most energy friendly microcontrollers transmit shift register is empty and ready for new data, the byte from the transmit buffer is then loaded into the shift register. The byte is then kept in the shift register until it is transmitted. When a byte has been transmitted, a new byte is loaded into the shift register (if available in the transmit buffer).
Page 423: C Master State Machine
...the world's most energy friendly microcontrollers After the address has been transmitted, a sequence of bytes can be read from or written to the slave, depending on the value of the R/W bit (bit 0 in the address byte). If the bit was cleared, the master has entered a master transmitter role, where it now transmits data to the slave.
Page 424: C Interactions In Prioritized Order
...the world's most energy friendly microcontrollers 16.3.7.2 Interactions Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends on the current state the of the I C module.
Page 425 ...the world's most energy friendly microcontrollers set in a pending state, which can be read from the STATUS register. A pending START command can for instance be identified by PSTART having a high value. Whenever the I C module requires an interaction, it checks the pending commands. If one or a combination of these can fulfill an interaction, they are consumed by the module and the transmission continues without setting the BUSHOLD interrupt flag in I2Cn_IF to get an interaction from software.
Page 426 ...the world's most energy friendly microcontrollers value of I2Cn_STATE will then be 0x57. As seen in the table, the I C module also stops in this state if the address is not available after a repeated start condition. To continue, write a byte to I2Cn_TXDATA with the address of the slave in the 7 most significant bits and the least significant bit cleared (ADDR+W).
Page 427 ...the world's most energy friendly microcontrollers I2Cn_STATE Description I2Cn_IF Required Response interaction START Repeated start condition will be sent STOP + STOP will be sent and the bus released. Then START a START will be sent when the bus becomes idle Data transmitted TXBL interrupt flag...
Page 428 ...the world's most energy friendly microcontrollers As when operating as a master transmitter, arbitration can be lost as a master receiver. When this happens the ARBLOST interrupt flag in I2Cn_IF is set, and the master has a possibility of being selected as a slave given the correct conditions.
Page 429 ...the world's most energy friendly microcontrollers I2Cn_STATE Description I2Cn_IF Required Response interaction START START will be sent when bus becomes idle Arbitration lost ARBLOST interrupt None flag START START will be sent when bus becomes idle 16.3.8 Bus States The I2Cn_STATE register can be used to determine which state the I C module and the I C bus are in at a given time.
Page 430: C Slave State Machine
...the world's most energy friendly microcontrollers 16.3.9.1 Slave State Machine The slave state machine is shown in Figure 16.11 (p. 430) . The dotted lines show where I C-specific interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission proceed.
Page 431 ...the world's most energy friendly microcontrollers 16.3.9.3 Slave Transmitter When SLAVE in I2Cn_CTRL is set, the RSTART interrupt flag in I2Cn_IF will be set when repeated START conditions are detected. After a START or repeated START condition, the bus master will transmit an address along with an R/W bit.
Page 432 ...the world's most energy friendly microcontrollers Table 16.9. I C Slave Transmitter I2Cn_STATE Description I2Cn_IF Required Response interaction 0x41 Repeated START RSTART interrupt flag RXDATA Receive and compare address received (BUSHOLD interrupt flag) 0x75 ADDR + R received ADDR interrupt flag ACK + ACK will be sent, then DATA TXDATA...
Page 433 ...the world's most energy friendly microcontrollers See Table 16.10 (p. 433) for more information. Table 16.10. I C - Slave Receiver I2Cn_STATE Description I2Cn_IF Required Response interaction Repeated START RSTART interrupt flag RXDATA Receive and compare address received (BUSHOLD interrupt flag) 0x71 ADDR + W received...
Page 434 ...the world's most energy friendly microcontrollers 16.3.11 Using 10-bit Addresses When using 10-bit addresses in slave mode, set the I2Cn_SADDR register to 1111 0XX where XX are the two most significant bits of the 10-bit address, and set I2Cn_SADDRMASK to 0xFF. Address matches will now be given on all 10-bit addresses where the two most significant bits are correct.
Page 435 ...the world's most energy friendly microcontrollers Many slave-only devices operating on an I C-bus are not capable of driving SCL low, but in the rare case that SCL is stuck LOW, the advice is to apply a hardware reset signal to the slaves on the bus. If this does not work, cycle the power to the devices in order to make them release SCL.
Page 436 ...the world's most energy friendly microcontrollers • Transmit buffer and shift register empty. No data to send • Transmit buffer empty 16.3.14 Interrupts The interrupts generated by the I C module are combined into one interrupt vector, I2C_INT. If I interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in I2Cn_IF and their corresponding bits in I2Cn_IEN are set.
Page 437: Register Map
...the world's most energy friendly microcontrollers 16.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 I2Cn_CTRL Control Register 0x004 I2Cn_CMD Command Register 0x008 I2Cn_STATE State Register 0x00C I2Cn_STATUS Status Register 0x010 I2Cn_CLKDIV Clock Division Register...
Page 438 ...the world's most energy friendly microcontrollers Name Reset Access Description When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated. Value Description A bus idle timeout has no effect on the bus state. A bus idle timeout tells the I C module that the bus is idle, allowing new transfers to be initiated.
Page 439 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description Software must give one ACK command for each ACK transmitted on the I C bus. Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. SLAVE Addressable as Slave Set this bit to allow the device to be selected as an I C slave.
Page 440 ...the world's most energy friendly microcontrollers 16.5.3 I2Cn_STATE - State Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) STATE Transmission State The state of any current transmission.
Page 441 ...the world's most energy friendly microcontrollers Name Reset Access Description RXDATAV RX Data Valid Set when data is available in the receive buffer. Cleared when the receive buffer is empty. TXBL TX Buffer Level Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full. TX Complete Set when a transmission has completed and no more data is available in the transmit buffer.
Page 442 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ADDR 0x00 Slave address Specifies the slave address of the device. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 443 ...the world's most energy friendly microcontrollers 16.5.9 I2Cn_RXDATAP - Receive Buffer Data Peek Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXDATAP 0x00 RX Data Peek...
Page 444 ...the world's most energy friendly microcontrollers Name Reset Access Description Set on each clock low timeout. The timeout value can be set in CLTO bit field in the I2Cn_CTRL register. BITO Bus Idle Timeout Interrupt Flag Set on each bus idle timeout. The timeout value can be set in the BITO bit field in the I2Cn_CTRL register. RXUF Receive Buffer Underflow Interrupt Flag Set when data is read from the receive buffer through the I2Cn_RXDATA register while the receive buffer is empty.
Page 445 ...the world's most energy friendly microcontrollers Name Reset Access Description SSTOP Set SSTOP Interrupt Flag Write to 1 to set the SSTOP interrupt flag. CLTO Set Clock Low Interrupt Flag Write to 1 to set the CLTO interrupt flag. BITO Set Bus Idle Timeout Interrupt Flag Write to 1 to set the BITO interrupt flag.
Page 446 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to clear the SSTOP interrupt flag. CLTO Clear Clock Low Interrupt Flag Write to 1 to clear the CLTO interrupt flag. BITO Clear Bus Idle Timeout Interrupt Flag Write to 1 to clear the BITO interrupt flag.
Page 447 ...the world's most energy friendly microcontrollers Name Reset Access Description CLTO Clock Low Interrupt Enable Enable interrupt on clock low timeout. BITO Bus Idle Timeout Interrupt Enable Enable interrupt on bus idle timeout. RXUF Receive Buffer Underflow Interrupt Enable Enable interrupt on receive buffer underflow. TXOF Transmit Buffer Overflow Interrupt Enable Enable interrupt on transmit buffer overflow.
Page 448 ...the world's most energy friendly microcontrollers Name Reset Access Description 10:8 LOCATION I/O Location Decides the location of the I C I/O pins. Value Mode Description LOC0 Location 0 LOC1 Location 1 LOC2 Location 2 LOC3 Location 3 LOC4 Location 4 LOC5 Location 5 LOC6...
Page 449: Usart - Universal Synchronous Asynchronous Receiver/Transmitter
...the world's most energy friendly microcontrollers 17 USART - Universal Synchronous Asynchronous Receiver/Transmitter Quick Facts What? 0 1 2 3 The USART handles high-speed UART, SPI- bus, SmartCards, and IrDA communication. Why? Serial communication is frequently used in embedded systems and the USART allows controller efficient communication with a wide range of external devices.
Page 450: Functional Description
...the world's most energy friendly microcontrollers • HW parity bit generation and check • Configurable number of stop bits in asynchronous mode: 0.5, 1, 1.5, 2 • HW collision detection • Multi-processor mode • IrDA modulator on USART0 • SmartCard (ISO7816) mode •...
Page 451: Usart Asynchronous Frame Format
...the world's most energy friendly microcontrollers Asynchronous or synchronous mode can be selected by configuring SYNC in USARTn_CTRL. The options are listed with supported protocols in Table 17.1 (p. 451) . Full duplex and half duplex communication is supported in both asynchronous and synchronous mode. Table 17.1.
Page 452: Usart Data Bits
...the world's most energy friendly microcontrollers Table 17.3. USART Data Bits DATA BITS [3:0] Number of Data bits 0001 0010 0011 0100 0101 8 (Default) 0110 0111 1000 1001 1010 1011 1100 1101 Table 17.4. USART Stop Bits STOP BITS [1:0] Number of Stop bits 1 (Default) The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL.
Page 453: Usart Baud Rate
...the world's most energy friendly microcontrollers Table 17.5. USART Parity Bits STOP BITS [1:0] Description No parity bit (Default) Reserved Even parity Odd parity 17.3.2.2 Clock Generation The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is given by Equation 17.1 (p.
Page 454 ...the world's most energy friendly microcontrollers Table 17.7. USART Baud Rates @ 4MHz Peripheral Clock USARTn_OVS =00 USARTn_OVS =01 Desired baud rate Actual baud Actual baud USARTn_CLKDIV/256 Error % USARTn_CLKDIV/256 Error % [baud/s] rate [baud/s] rate [baud/s] 415,75 599,88 -0,02 832,25 600,06 0,01...
Page 455 ...the world's most energy friendly microcontrollers frames, complete with control bits to be written at once. When data is written to the transmit buffer using USARTn_TXDATAX and USARTn_TXDOUBLEX, the 9th bit(s) written to these registers override the value in BIT8DV in USARTn_CTRL, and alone define the 9th bits that are transmitted if 9-bit frames are used.
Page 456 ...the world's most energy friendly microcontrollers • Tristate transmitter after transmission: If TXTRIAT is set, TXTRI is set after the frame has been fully transmitted, tristating the transmitter output. Tristating of the output can also be performed automatically by setting AUTOTRI. If AUTOTRI is set TXTRI is always read as 0. Note When in SmartCard mode with repeat enabled, none of the actions, except generate break, will be performed until the frame is transmitted without failure.
Page 457 ...the world's most energy friendly microcontrollers The basic operation of the receive buffer when DATABITS in USARTn_FRAME is configured to less than 10 bits is shown in Figure 17.4 (p. 457) . Figure 17.4. USART Receive Buffer Operation Peripheral Bus RXDOUBLE RXDATA, RXDOUBLEX...
Page 458: Usart Sampling Of Start And Data Bits
...the world's most energy friendly microcontrollers When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate generator is synchronized with the incoming frame. For oversampling modes 16, 8 and 6, every bit in the incoming frame is sampled three times to gain a level of noise immunity.
Page 459: Usart Sampling Of Stop Bits When Number Of Stop Bits Are 1 Or More
...the world's most energy friendly microcontrollers Figure 17.6. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More n’th bit 1 stop bit Idle or start bit 13 14 15 16 1 9 10 0/ 1 0/ 1 0/ 1 0/ 1...
Page 460 ...the world's most energy friendly microcontrollers can receive the data it transmits, but it is also used to allow the USART to read and write to the same pin, which is required for some half duplex communication modes. In this mode, the U(S)n_TX pin must be enabled as an output in the GPIO.
Page 461 ...the world's most energy friendly microcontrollers This can be done manually by assigning a GPIO to turn the driver on or off, or it can be handled automatically by the USART. If AUTOCS in USARTn_CTRL is set, the USn_CS output is automatically activated one baud period before the transmitter starts transmitting data, and deactivated when the last bit has been transmitted and there is no more data in the transmit buffer to transmit, or the transmitter becomes disabled.
Page 462: Usart Transmission Of Large Frames
...the world's most energy friendly microcontrollers Figure 17.9. USART Transmission of Large Frames Peripheral Bus TX buffer elem ent 1 Write CTRL TX buffer elem ent 0 Write CTRL Shift register Write CTRL As shown in Figure 17.9 (p. 462) , frame transmission control bits are taken from the second element in FIFO.
Page 463 ...the world's most energy friendly microcontrollers Figure 17.11. USART Reception of Large Frames Peripheral Bus RX buffer elem ent 0 Status RX buffer elem ent 1 Status Shift register Status The two buffer elements can be read at the same time using the USARTn_RXDOUBLE or USARTn_RXDOUBLEX register.
Page 464: Usart Iso 7816 Data Frame Without Error
...the world's most energy friendly microcontrollers BIT8DV in USARTn_CTRL can be used to specify the value of the 9th bit without writing to the transmit buffer with USARTn_TXDATAX or USARTn_TXDOUBLEX, giving higher efficiency in multi-processor mode, as the 9th bit is only set when writing address frames, and 8-bit writes to the USART can be used when writing the data frames.
Page 465: Usart Iso 7816 Data Frame With Error
...the world's most energy friendly microcontrollers Figure 17.13. USART ISO 7816 Data Frame With Error ISO 7816 Fram e with error Start or idle Stop or idle Stop Stop On a parity error, the NAK is generated by hardware. The NAK generated by the receiver is sampled as the stop-bit of the frame.
Page 466: Usart Spi Modes
...the world's most energy friendly microcontrollers 17.3.3.1 Frame Format The frames used in synchronous mode need no start and stop bits since a single clock is available to all parts participating in the communication. Parity bits cannot be used in synchronous mode. The USART supports frame lengths of 4 to 16 bits per frame.
Page 467 ...the world's most energy friendly microcontrollers Figure 17.15. USART SPI Timing CLKPOL = 0 USn_CLK CLKPOL = 1 USn_CS CLKPHA = 0 USn_TX/ USn_RX CLKPHA = 1 If CPHA=1, the TX underflow flag, TXUF, will be set on the first setup clock edge of a frame in slave mode if TX data is not available.
Page 468 ...the world's most energy friendly microcontrollers When AUTOTX in USARTn_CTRL is set, the USART transmits data as long as there is available space in the RX shift register for the chosen frame size. This happens even though there is no data in the TX buffer.
Page 469: Usart I2S Modes
...the world's most energy friendly microcontrollers whether the transmitted word is for the left or right audio channel; A word transmitted while the word clock is low is for the left channel, and a word transmitted while the word clock is high is for the right. When operating in I2S mode, the CS pin is used as a the word clock.
Page 470 ...the world's most energy friendly microcontrollers Figure 17.17. USART Standard I2S waveform (reduced accuracy) USn_CLK USn_CS (word select) USn_TX/ USn_RX Right channel Left channel Right channel A left-justified stream is shown in Figure 17.18 (p. 470) . Note that the MSB comes directly after the edge on the word-select signal in contradiction to the regular I2S waveform where it comes one bit- period after.
Page 471 ...the world's most energy friendly microcontrollers In mono-mode, the word-select signal pulses at the beginning of each word instead of toggling for each word. Mono I2S waveform is shown in Figure 17.20 (p. 471) . Figure 17.20. USART Mono I2S waveform USn_CLK USn_CS (word select)
Page 472 ...the world's most energy friendly microcontrollers TX buffer with the command and enable AUTOTXTEN and TXTEN. When the selected PRS input goes high, the USART will now transmit the loaded command, and then continue clocking out while both the PRS input is high and there is room in the RX buffer 17.3.5 PRS RX Input The USART can be configured to receive data directly from a PRS channel by setting RXPRS in USARTn_INPUT.
Page 473 ...the world's most energy friendly microcontrollers The transmission interrupt vector groups the transmission-related interrupts generated by the following interrupt flags: • TXC • TXBL • TXOF • CCF The reception interrupt on the other hand groups the reception-related interrupts, triggered by the following interrupt flags: •...
Page 474 ...the world's most energy friendly microcontrollers Table 17.10. USART IrDA Pulse Widths IRPW Pulse width OVS=0 Pulse width OVS=1 Pulse width OVS=2 Pulse width OVS=3 1/16 2/16 3/16 4/16 By default, no filter is enabled in the IrDA demodulator. A filter can be enabled by setting IRFILT in USARTn_IRCTRL.
Page 475: Register Map
...the world's most energy friendly microcontrollers 17.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 USARTn_CTRL Control Register 0x004 USARTn_FRAME USART Frame Format Register 0x008 USARTn_TRIGCTRL USART Trigger Control register 0x00C USARTn_CMD Command Register...
Page 476 ...the world's most energy friendly microcontrollers Name Reset Access Description Transmits as long as RX is not full. If TX is empty, underflows are generated. BYTESWAP Byteswap In Double Accesses Set to switch the order of the bytes in double accesses. Value Description Normal byte order...
Page 477 ...the world's most energy friendly microcontrollers Name Reset Access Description Default value is active low. This affects both the selection of external slaves, as well as the selection of the microcontroller as a slave. Value Description Chip select is active low Chip select is active high TXINV Transmitter output Invert...
Page 478 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description Double speed with 8X oversampling in asynchronous mode 6X oversampling in asynchronous mode Quadruple speed with 4X oversampling in asynchronous mode MPAB Multi-Processor Address-Bit Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame as a multi-processor address frame.
Page 479 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description The transmitter generates two stop bits. The receiver checks the first stop-bit only 11:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PARITY Parity-Bit Mode Determines whether parity bits are enabled, and whether even or odd parity should be used.
Page 480 ...the world's most energy friendly microcontrollers Name Reset Access Description Select USART PRS trigger channel. The PRS signal can enable RX and/or TX, depending on the setting of RXTEN and TXTEN. Value Mode Description PRSCH0 PRS Channel 0 selected PRSCH1 PRS Channel 1 selected PRSCH2 PRS Channel 2 selected...
Page 481 ...the world's most energy friendly microcontrollers Name Reset Access Description RXEN Receiver Enable Set to activate data reception on U(S)n_RX. 17.5.5 USARTn_STATUS - USART Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXFULLRIGHT RX Full of Right Data When set, the entire RX buffer contains right data.
Page 482 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when the receiver is enabled. 17.5.6 USARTn_CLKDIV - Clock Control Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:6 0x0000 Fractional Clock Divider...
Page 483 ...the world's most energy friendly microcontrollers 17.5.8 USARTn_RXDATA - RX Buffer Data Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXDATA 0x00 RX Data...
Page 484 ...the world's most energy friendly microcontrollers 17.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:8 RXDATA1 0x00...
Page 485 ...the world's most energy friendly microcontrollers 17.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description FERRP1 Data Framing Error 1 Peek Set if data in buffer has a framing error. Can be the result of a break condition. PERRP1 Data Parity Error 1 Peek Set if data in buffer has a parity error (asynchronous mode only).
Page 486 ...the world's most energy friendly microcontrollers Name Reset Access Description Set to disable transmitter and release data bus directly after transmission. TXBREAK Transmit Data As Break Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA.
Page 487 ...the world's most energy friendly microcontrollers Name Reset Access Description Set to disable transmitter and release data bus directly after transmission. TXBREAK1 Transmit Data As Break Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value of USARTn_TXDATA.
Page 488 ...the world's most energy friendly microcontrollers 17.5.17 USARTn_IF - Interrupt Flag Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Collision Check Fail Interrupt Flag Set when a collision check notices an error in the transmitted data.
Page 489 ...the world's most energy friendly microcontrollers 17.5.18 USARTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Set Collision Check Fail Interrupt Flag Write to 1 to set the CCF interrupt flag.
Page 490 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Clear Collision Check Fail Interrupt Flag Write to 1 to clear the CCF interrupt flag. Clear Slave-Select In Master Mode Interrupt Flag Write to 1 to clear the SSM interrupt flag.
Page 491 ...the world's most energy friendly microcontrollers Name Reset Access Description Enable interrupt on framing error. PERR Parity Error Interrupt Enable Enable interrupt on parity error (asynchronous mode only). TXUF TX Underflow Interrupt Enable Enable interrupt on TX underflow. TXOF TX Overflow Interrupt Enable Enable interrupt on TX overflow.
Page 492 ...the world's most energy friendly microcontrollers Name Reset Access Description Set to enable filter on IrDA demodulator. Value Description No filter enabled Filter enabled. IrDA pulse must be high for at least 4 consecutive clock cycles to be detected IRPW IrDA TX Pulse Width Configure the pulse width generated by the IrDA modulator as a fraction of the configured USART bit period.
Page 493 ...the world's most energy friendly microcontrollers Name Reset Access Description TXPEN TX Pin Enable When set, the TX/MOSI pin of the USART is enabled Value Description The U(S)n_TX (MOSI) pin is disabled The U(S)n_TX (MOSI) pin is enabled RXPEN RX Pin Enable When set, the RX/MISO pin of the USART is enabled.
Page 494 ...the world's most energy friendly microcontrollers 17.5.24 USARTn_I2SCTRL - I2S Control Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 FORMAT I2S Word Format...
Page 495: Uart - Universal Asynchronous Receiver/Transmitter
...the world's most energy friendly microcontrollers 18 UART - Universal Asynchronous Receiver/ Transmitter Quick Facts What? 0 1 2 3 The UART is capable of high-speed asynchronous serial communication. Why? Serial communication is frequently used in embedded systems and the UART allows efficient communication with a wide range of controller external devices.
Page 496: Functional Description
...the world's most energy friendly microcontrollers • Communication debugging • PRS can trigger transmissions • Full DMA support • PRS RX input 18.3 Functional Description The UART is functionally equivalent to the USART with the exceptions defined in Table 18.1 (p. 496) .
Page 497: Leuart - Low Energy Universal Asynchronous Receiver/Transmitter
...the world's most energy friendly microcontrollers 19 LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Quick Facts What? The LEUART provides full UART communication using a low frequency 32.768 0 1 2 3 kHz clock, and has special features for communication without CPU intervention. Why? It allows UART communication to be controller...
Page 498: Functional Description
...the world's most energy friendly microcontrollers • Can use a high frequency clock source for even higher baud rates • Configurable number of data bits: 8 or 9 (plus parity bit, if enabled) • Configurable parity: off, even or odd •...
Page 499 ...the world's most energy friendly microcontrollers low for one bit-period. This signals the start of a frame, and is used for synchronization. Following the start bit are 8 or 9 data bits and an optional parity bit. The data is transmitted with the least significant bit first.
Page 500: Leuart Baud Rates
...the world's most energy friendly microcontrollers The clock divider used in the LEUART is a 12-bit value, with a 7-bit integral part and a 5-bit fractional part. The baud rate of the LEUART is given by : LEUART Baud Rate Equation br = fLEUARTn/(1 + LEUARTn_CLKDIV/256) (19.1) where fLEUARTn is the clock frequency supplied to the LEUART.
Page 501 ...the world's most energy friendly microcontrollers If a write is attempted to the transmit buffer when it is not empty, the TXOF interrupt flag in LEUARTn_IF is set, indicating the overflow. The data already in the buffer is in that case preserved, and no data is written.
Page 502 ...the world's most energy friendly microcontrollers 19.3.4.3 Jitter in Transmitted Data Internally the LEUART module uses only the positive edges of the 32.768 kHz clock (LFBCLK) for transmission and reception. Transmitted data will thus have jitter equal to the difference between the optimal data set-up location and the closest positive edge on the 32.768 kHz clock.
Page 503 ...the world's most energy friendly microcontrollers Figure 19.4. LEUART Receiver Overview RXDATA RXENS !RXBLOCK Receive shift register LEUn_RX d0- d8 status status Receive buffer RXDATAX (RXDATAXP) 19.3.5.2 Blocking Incoming Data When using hardware frame recognition, as detailed in Section 19.3.5.6 (p. 504) , Section 19.3.5.7 (p. 505) , and Section 19.3.5.8 (p.
Page 504: Leuart Optimal Sampling Point
...the world's most energy friendly microcontrollers LEUART Optimal Sampling Point (n) = n (1 + LEUARTn_CLKDIV/256) + CLKDIV/512 (19.3) where n is the bit-index. Since samples are only done on the positive edges of the 32.768 kHz clock, the actual samples are performed on the closest positive edge, i.e.
Page 505 ...the world's most energy friendly microcontrollers When 8 data-bit frame formats are used, only the 8 least significant bits of LEUARTn_STARTFRAME are compared to incoming frames. The full length of LEUARTn_STARTFRAME is used when operating with frames consisting of 9 data bits. Note The receiver must be enabled for start frames to be detected.
Page 506 ...the world's most energy friendly microcontrollers Figure 19.5. LEUART Local Loopback LOOPBK = 0 LOOPBK = 1 µC µC LEUART LEUART LEUn_TX LEUn_TX LEUn_RX LEUn_RX 19.3.7 Half Duplex Communication When doing full duplex communication, two data links are provided, making it possible for data to be sent and received at the same time.
Page 507 ...the world's most energy friendly microcontrollers 19.3.7.3 Two Data-links Some limited devices only support half duplex communication even though two data links are available. In this case software is responsible for making sure data is not transmitted when incoming data is expected.
Page 508 ...the world's most energy friendly microcontrollers EM2/EM3 before the frame has been read from the LEUART. In order for the system to go to EM2 during the last byte transmission, LEUART_CTRL_TXDMAWU must be cleared in the DMA interrupt service routine. This is because TXBL will be high during that last byte transfer.
Page 509: Register Map
...the world's most energy friendly microcontrollers 19.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LEUARTn_CTRL Control Register 0x004 LEUARTn_CMD Command Register 0x008 LEUARTn_STATUS Status Register 0x00C LEUARTn_CLKDIV Clock Control Register 0x010 LEUARTn_STARTFRAME Start Frame Register...
Page 510 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description TRIPLE Transmission of new frames are delayed by three baud periods TXDMAWU TX DMA Wakeup Set to wake the DMA controller up when in EM2 and space is available in the transmit buffer. Value Description While in EM2, the DMA controller will not get requests about space being available in the transmit buffer...
Page 511 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description One stop-bit is transmitted with every frame Two stop-bits are transmitted with every frame PARITY Parity-Bit Mode Determines whether parity bits are enabled, and whether even or odd parity should be used. Value Mode Description...
Page 512 ...the world's most energy friendly microcontrollers Name Reset Access Description RXDIS Receiver Disable Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded. RXEN Receiver Enable Set to activate data reception on LEUn_RX. 19.5.3 LEUARTn_STATUS - Status Register Offset Bit Position...
Page 513 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 14:3 0x000 Fractional Clock Divider Specifies the fractional clock divider for the LEUART. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 514 ...the world's most energy friendly microcontrollers 19.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) FERR Receive Data Framing Error Set if data in buffer has a framing error.
Page 515 ...the world's most energy friendly microcontrollers 19.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) FERRP Receive Data Framing Error Peek Set if data in buffer has a framing error.
Page 516 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description The transmitter is disabled, clearing TXENS after the frame has been transmitted TXBREAK Transmit Data As Break Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA.
Page 517 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when a multi-processor address frame is detected. FERR Framing Error Interrupt Flag Set when a frame with a framing error is received while RXBLOCK is cleared. PERR Parity Error Interrupt Flag Set when a frame with a parity error is received while RXBLOCK is cleared.
Page 518 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to set the RXOF interrupt flag. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Set TX Complete Interrupt Flag Write to 1 to set the TXC interrupt flag.
Page 519 ...the world's most energy friendly microcontrollers 19.5.15 LEUARTn_IEN - Interrupt Enable Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SIGF Signal Frame Interrupt Enable Enable interrupt on signal frame.
Page 520 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PULSEFILT Pulse Filter Enable a one-cycle pulse filter for pulse extender Value Description Filter is disabled.
Page 521 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when the value written to TXDATA is being synchronized. TXDATAX TXDATAX Register Busy Set when the value written to TXDATAX is being synchronized. SIGFRAME SIGFRAME Register Busy Set when the value written to SIGFRAME is being synchronized. STARTFRAME STARTFRAME Register Busy Set when the value written to STARTFRAME is being synchronized.
Page 522 ...the world's most energy friendly microcontrollers 19.5.20 LEUARTn_INPUT - LEUART Input Register Offset Bit Position 0x0AC Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXPRS PRS RX Enable When set, the PRS channel selected as input to RX.
Page 523: Timer - Timer/Counter
...the world's most energy friendly microcontrollers 20 TIMER - Timer/Counter Quick Facts What? 0 1 2 3 The TIMER (Timer/Counter) keeps track of timing and counts events, generates output waveforms and triggers timed actions in other peripherals. Why? USART Most applications have activities that need to be timed accurately with as little CPU intervention and energy consumption as TIMER...
Page 524: Functional Description
...the world's most energy friendly microcontrollers • Period measurement • Pulse width measurement • Two capture registers for each capture channel • Capture on either positive or negative edge • Capture on both edges • Optional digital noise filtering on capture inputs •...
Page 525 ...the world's most energy friendly microcontrollers Figure 20.1. TIMER Block Overview HFPERCLK Prescaler CNTCLK TIMERn Note: For sim plicity, all Counter TIMERn_CCx registers are control Update grouped together in the figure, condition but they all have individual Input Capture Registers TIMERn_CNT TIMERn_TOP Quadrature...
Page 526 ...the world's most energy friendly microcontrollers It is also possible to control the counter through either an external pin or PRS input. This is done through the input logic for the Compare/Capture Channel 0. The Timer/Counter allows individual actions (start, stop, reload) to be taken for rising and falling input edges.
Page 527 ...the world's most energy friendly microcontrollers However, if 2x Count Mode is enabled and the Compare/Capture channels are put in PWM mode, the CC output is updated on both clock edges so prescaling the peripheral clock will result in incorrect result. The prescaler is stopped and reset when the timer is stopped.
Page 528 ...the world's most energy friendly microcontrollers 20.3.1.6 Quadrature Decoder Quadrature Decoding mode is used to track motion and determine both rotation direction and position. The Quadrature Decoder uses two input channels that are 90 degrees out of phase (see Figure 20.6 (p. 528) ).
Page 529: Timer Counter Response In X2 Decoding Mode
...the world's most energy friendly microcontrollers 20.3.1.6.1 X2 Decoding Mode In X2 Decoding mode, the counter increments or decrements on every edge of Channel A, see Table 20.1 (p. 529) and Figure 20.8 (p. 529) . Table 20.1. TIMER Counter Response in X2 Decoding Mode Channel A Channel B Rising...
Page 530 ...the world's most energy friendly microcontrollers pos° = (CNT/X x N) x 360° (20.1) where X = Encoding type and N = Number of pulses per revolution. 20.3.2 Compare/Capture Channels The Timer contains 3 Compare/Capture channels, which can be configured in the following modes: 1.
Page 531 ...the world's most energy friendly microcontrollers Figure 20.11. TIMER Input Capture Buffer Functionality CCVB FIFO 20.3.2.2.2 Compare and PWM Mode When running in Output Compare or PWM mode, the value in TIMERn_CCx_CCV will be compared against the count value. In Compare mode the output can be configured to toggle, clear or set on compare match, overflow and underflow through the CMOA, COFOA and CUFOA fields in TIMERn_CCx_CTRL.
Page 532 ...the world's most energy friendly microcontrollers Figure 20.13. TIMER Input Capture Input TIMERn_CNT TIMERn_CCx _CCV prev. val prev. val TIMERn_CCx _CCVB Read TIMERn_CCx _CCVB 20.3.2.3.1 Period/Pulse-Width Capture Period and/or pulse-width capture can be achieved by setting the RISEA field in TIMERn_CTRL to Clear&Start, and select the wanted input from either external pin or PRS, see Figure 20.14 (p.
Page 533 ...the world's most energy friendly microcontrollers Figure 20.15. TIMER Block Diagram Showing Comparison Functionality Update Condition CNTCLK TIMERn_CNT TIMERn_TOP Overflow Underflow Note: For sim plicity, all TIMERn_CCx registers are grouped together in the figure, Com pare Match x but they all have individual Com pare Register and logic Com pare and TnCCR1[15:0...
Page 534: Timer Up-Count Pwm Resolution Equation
...the world's most energy friendly microcontrollers Figure 20.17. TIMER Up-count Frequency Generation TIMERn_TOP TIMERn_CCx _CCV The output frequency is given by Equation 20.2 (p. 534) TIMER Up-count Frequency Generation Equation / ( 2^(PRESC + 1) x (TOP + 1) x 2) (20.2) HFPERCLK 20.3.2.5 Pulse-Width Modulation (PWM)
Page 535: Timer Up-Count Duty Cycle Equation
...the world's most energy friendly microcontrollers TIMER Up-count Duty Cycle Equation = CCVx/TOP (20.5) 20.3.2.6.1 2x Count Mode When the Timer is set in 2x mode, the TIMER will count up by two. This will in effect make any odd Top value be rounded down to the closest even number.
Page 536: Timer Up/Down-Count Pwm Resolution Equation
...the world's most energy friendly microcontrollers Figure 20.20. TIMER Up/Down-count PWM Generation TIMERn_TOP TIMERn_CCx _CCV TIMn_CCx Overflow Com pare m atch Buffer update TIMER Up/Down-count PWM Resolution Equation = log(TOP+1)/log(2) (20.9) up/down The PWM frequency is given by Equation 20.10 (p. 536) : TIMER Up/Down-count PWM Frequency Equation / ( 2^(PRESC+1) x TOP) (20.10)
Page 537: Timer 2X Mode Pwm Frequency Equation( Up/Down-Count)
...the world's most energy friendly microcontrollers The PWM frequency is given by Equation 20.7 (p. 535) : TIMER 2x Mode PWM Frequency Equation( Up/Down-count) / TOP (20.13) HFPERCLK 2xmode The high duty cycle is given by Equation 20.14 (p. 537) TIMER 2x Mode Duty Cycle Equation = CCVx/TOP (20.14)
Page 538 ...the world's most energy friendly microcontrollers control of e.g. 3-channel BLDC or PMAC motors possible using only a single timer, see Figure 20.24 (p. 538) . Figure 20.24. TIMER Overview of Dead-Time Insertion Block for a Single PWM channel DTFALLT DTRISET Select Original PWM (TIM0_CCx _pre)
Page 539 ...the world's most energy friendly microcontrollers Example 20.1. TIMER DTI Example 1 DTIPOL = 0 and DTCINV = 0 results in outputs with opposite phase and active-high states. Example 20.2. TIMER DTI Example 2 DTIPOL = 1 and DTCINV = 1 results in outputs with equal phase. The primary output will be active-high, while the complementary will be active-low Figure 20.26.
Page 540 ...the world's most energy friendly microcontrollers The fault sources which trigger a fault in the DTI module are determined by TIMER0_DTFSEN. Any combination of the available error sources can be selected: • PRS source 0, determined by DTPRS0FSEL in TIMER0_DTFC •...
Page 541: Timer Events
...the world's most energy friendly microcontrollers • Counter Underflow • Counter Overflow • Compare match or input capture (one per Compare/Capture channel) Each of the events has its own interrupt flag. Also, there is one interrupt flag for each Compare/Capture channel which is set on buffer overflow in capture mode.
Page 542: Register Map
...the world's most energy friendly microcontrollers 20.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 TIMERn_CTRL Control Register 0x004 TIMERn_CMD Command Register 0x008 TIMERn_STATUS Status Register 0x00C TIMERn_IEN Interrupt Enable Register 0x010 TIMERn_IF Interrupt Flag Register...
Page 543: Register Description
...the world's most energy friendly microcontrollers 20.5 Register Description 20.5.1 TIMERn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RSSCOIST Reload-Start Sets Compare Output initial State When enabled, compare output is set to COIST value at Reload-Start event...
Page 544 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description STOP Stop counter without reload RELOADSTART Reload and start counter RISEA Timer Rising Input Edge Action These bits select the action taken in the counter when a rising edge occurs on the input. Value Mode Description...
Page 545 ...the world's most energy friendly microcontrollers 20.5.2 TIMERn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) STOP Stop Timer Write a 1 to this bit to stop timer...
Page 546 ...the world's most energy friendly microcontrollers Name Reset Access Description 23:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ICV2 CC2 Input Capture Valid This bit indicates that TIMERn_CC2_CCV contains a valid capture value. These bits are only used in input capture mode and are cleared when CCMODE is written to 0b00 (Off).
Page 547 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DOWN Counting down RUNNING Running Indicates if timer is running or not. 20.5.4 TIMERn_IEN - Interrupt Enable Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:11...
Page 548 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ICBOF2 CC Channel 2 Input Capture Buffer Overflow Interrupt Flag This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC2_CCV/TIMERn_CC2_CCVB register pair.
Page 549 ...the world's most energy friendly microcontrollers Name Reset Access Description Writing a 1 to this bit will set Compare/Capture channel 1 interrupt flag. CC Channel 0 Interrupt Flag Set Writing a 1 to this bit will set Compare/Capture channel 0 interrupt flag. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 550 ...the world's most energy friendly microcontrollers 20.5.8 TIMERn_TOP - Counter Top Value Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0xFFFF Counter Top Value...
Page 551 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0x0000 Counter Value These bits hold the counter value. 20.5.11 TIMERn_ROUTE - I/O Routing Register Offset Bit Position...
Page 552 ...the world's most energy friendly microcontrollers 20.5.12 TIMERn_CCx_CTRL - CC Channel Control Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 27:26 ICEVCTRL Input Capture Event Control...
Page 553 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PRSCH8 PRS Channel 8 selected as input PRSCH9 PRS Channel 9 selected as input PRSCH10 PRS Channel 10 selected as input PRSCH11 PRS Channel 11 selected as input 15:14 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 554 ...the world's most energy friendly microcontrollers 20.5.13 TIMERn_CCx_CCV - CC Channel Value Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0x0000 CC Channel Value...
Page 555 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 CCVB 0x0000 CC Channel Value Buffer In Input Capture mode, this field holds the last capture value if the TIMERn_CCx_CCV register already contains an earlier unread capture value.
Page 556 ...the world's most energy friendly microcontrollers 20.5.17 TIMERn_DTTIME - DTI Time Control Register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 21:16 DTFALLT 0x00...
Page 557 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DTLOCKUPFEN DTI Lockup Fault Enable Set this bit to 1 to enable core lockup as a fault source DTDBGFEN DTI Debugger Fault Enable Set this bit to 1 to enable debugger as a fault source...
Page 558 ...the world's most energy friendly microcontrollers 20.5.19 TIMERn_DTOGEN - DTI Output Generation Enable Register Offset Bit Position 0x07C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DTOGCDTI2EN DTI CDTI2 Output Generation Enable This bit enables/disables output generation for the CDTI2 output from the DTI.
Page 559 ...the world's most energy friendly microcontrollers Name Reset Access Description DTPRS0F DTI PRS 0 Fault This bit is set to 1 if a PRS 0 fault has occurred and DTPRS0FEN is set to 1. The TIMER0_DTFAULTC register can be used to clear fault bits.
Page 560 ...the world's most energy friendly microcontrollers Name Reset Access Description Mode Value Description Write Operation LOCK Lock TIMER DTI registers UNLOCK 0xCE80 Unlock TIMER DTI registers www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 561: Rtc - Real Time Counter
...the world's most energy friendly microcontrollers 21 RTC - Real Time Counter Quick Facts What? The Real Time Counter (RTC) ensures timekeeping in low energy modes. Combined with two low power oscillators (XTAL or RC), the RTC can run in EM2 with total current consumption less than 1.1 µA, and in EM3 0 1 2 3 with total current consumption less than 0.8...
Page 562: Functional Description
...the world's most energy friendly microcontrollers 21.3 Functional Description The RTC is a 24-bit counter with two compare channels. The RTC is closely coupled with the LETIMER, and can be configured to trigger it on a compare match on one or both compare channels. An overview of the RTC module is shown in Figure 21.1 (p.
Page 563 ...the world's most energy friendly microcontrollers Table 21.1. RTC Resolution Vs Overflow RTC_PRESC Resolution Overflow 30,5 µs 512 s 61,0 µs 1024 s 122 µs 2048 s 244 µs 1,14 hours 488 µs 2,28 hours 977 µs 4,55 hours 1,95 ms 9,10 hours 3,91 ms 18,2 hours...
Page 564 ...the world's most energy friendly microcontrollers 21.3.4 Debugrun By default, the RTC is halted when code execution is halted from the debugger. By setting the DEBUGRUN bit in the RTC_CTRL register, the RTC will continue to run even when the debugger is halted.
Page 565: Register Map
...the world's most energy friendly microcontrollers 21.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RTC_CTRL Control Register 0x004 RTC_CNT Counter Value Register 0x008 RTC_COMP0 Compare Value Register 0 0x00C RTC_COMP1 Compare Value Register 1 0x010...
Page 566 ...the world's most energy friendly microcontrollers 21.5.2 RTC_CNT - Counter Value Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 0x000000 Counter Value...
Page 567 ...the world's most energy friendly microcontrollers Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 COMP1 0x000000 Compare Value 1 A compare match event occurs when CNT is equal to this value.
Page 568 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) COMP1 Set Compare match 1 Interrupt Flag Write to 1 to set the COMP1 interrupt flag. COMP0 Set Compare match 0 Interrupt Flag Write to 1 to set the COMP0 interrupt flag.
Page 569 ...the world's most energy friendly microcontrollers Name Reset Access Description Enable interrupt on overflow. 21.5.9 RTC_FREEZE - Freeze Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) REGFREEZE Register Update Freeze When set, the update of the RTC is postponed until this bit is cleared.
Page 570: Burtc - Backup Real Time Counter
...the world's most energy friendly microcontrollers 22 BURTC - Backup Real Time Counter Quick Facts What? The Backup Real Time Counter (BURTC) allows timekeeping in all energy modes. Running on the LFXO, LFRCO, or ULFRCO, the BURTC can run in EM4 with a total current consumption less than 0.5uA.
Page 571: Functional Description
...the world's most energy friendly microcontrollers 22.3 Functional Description The Backup RTC is a 32-bit counter with one compare channel. The Backup RTC resides in a power domain which can be configured to always be on, in EM0 through EM4. This domain also has the possibility to be powered by a backup battery.
Page 572: Low Power Mode Compare Match Resolution
...the world's most energy friendly microcontrollers If COMP0TOP is cleared, the counter will continue counting, wrapping around when it overflows. On overflow, the OF interrupt flag is set. 22.3.4 PRS Sources The compare channel of the Backup RTC can be used as PRS source. A pulse lasting one clock cycle will be generated on a compare match.
Page 573 ...the world's most energy friendly microcontrollers Note Low power mode is only available when using LFXO or LFRCO. 22.3.7 Retention Registers The Backup RTC includes 128 x 32 bit registers with possible retention in all energy modes. The registers are accessible through the RETx_REG registers. Retention is by default enabled in EM0 through EM4. The registers can be shut off to save power by setting RAM in BURTC_POWERDOWN.
Page 574 ...the world's most energy friendly microcontrollers www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 575: Register Map
...the world's most energy friendly microcontrollers 22.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 BURTC_CTRL Control Register 0x004 BURTC_LPMODE Low power mode configuration 0x008 BURTC_CNT Counter Value Register 0x00C BURTC_COMP0 Counter Compare Value 0x010...
Page 576 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description LFRCO LFRCO selected as BURTC clock source. LFXO LFXO selected as BURTC clock source. ULFRCO ULFRCO selected as BURTC clock source. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 PRESC Select BURTC prescaler factor...
Page 577 ...the world's most energy friendly microcontrollers Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LPMODE Low power mode configuration. Value Mode Description...
Page 578 ...the world's most energy friendly microcontrollers Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:0 COMP0 0x00000000 Compare match value Gives access to the BURTC compare value. 22.5.5 BURTC_TIMESTAMP - Backup mode timestamp Offset Bit Position 0x010 Reset Access Name...
Page 579 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 0x00 LFXO failure counter top value. LFXO failure counter will wrap to this value when reaching zero. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 580 ...the world's most energy friendly microcontrollers Name Reset Access Description Clear RAMWERR and BUMODETS in BURTC_STATUS. 22.5.9 BURTC_POWERDOWN - Retention RAM power-down Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Retention RAM power-down Shut off power to the Retention RAM.
Page 581 ...the world's most energy friendly microcontrollers 22.5.11 BURTC_IF - Interrupt Flag Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LFXOFAIL LFXO failure Interrupt Flag Set on LFXO failure.
Page 582 ...the world's most energy friendly microcontrollers 22.5.13 BURTC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LFXOFAIL Clear LFXO failure Interrupt Flag Write to 1 to clear the LFXOFAIL interrupt flag...
Page 583 ...the world's most energy friendly microcontrollers 22.5.15 BURTC_FREEZE - Freeze Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) REGFREEZE Register Update Freeze When set, the update of the BURTC is postponed until this bit is cleared.
Page 584 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 0xXXXXXXXX General Purpose Retention Register www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 585: Letimer - Low Energy Timer
...the world's most energy friendly microcontrollers 23 LETIMER - Low Energy Timer Quick Facts What? The LETIMER is a down-counter that can keep track of time and output configurable waveforms. Running on a 32.768 Hz clock the LETIMER is available in EM2, while 0 1 2 3 using a 1 kHz clock the LETIMER is available also in EM3, all this with sub µA current...
Page 586: Functional Description
...the world's most energy friendly microcontrollers • Interrupt on: • Compare matches • Timer underflow • Repeat done • Optionally runs during debug • PRS Output 23.3 Functional Description An overview of the LETIMER module is shown in Figure 23.1 (p. 586) . The LETIMER is a 16-bit down-counter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1.
Page 587 ...the world's most energy friendly microcontrollers 23.3.2 Compare Registers The LETIMER has two compare match registers, LETIMERn_COMP0 and LETIMERn_COMP1. Each of these compare registers are capable of generating an interrupt when the counter value LETIMERn_CNT becomes equal to their value. When LETIMERn_CNT becomes equal to the value of LETIMERn_COMP0, the interrupt flag COMP0 in LETIMERn_IF is set, and when LETIMERn_CNT becomes equal to the value of LETIMERn_COMP1, the interrupt flag COMP1 in LETIMERn_IF is set.
Page 588 ...the world's most energy friendly microcontrollers 23.3.3.2.1 Free Mode In the free running mode, the LETIMER acts as a regular timer, and the repeat counter is disabled. When started, the timer runs until it is stopped using the STOP command bit in LETIMERn_CMD. A state machine for this mode is shown in Figure 23.2 (p.
Page 589 ...the world's most energy friendly microcontrollers Figure 23.3. LETIMER One-shot Repeat State Machine Wait for positive clock edge If (STOP) RUNNING = 0 RUNNING Else if (START) RUNNING = 1 End if START START = 0 STOP = 0 CNT = CNT - 1 CNT = = 0 CNT = = 0 CNT = CNT - 1...
Page 590 ...the world's most energy friendly microcontrollers Figure 23.4. LETIMER Buffered Repeat State Machine Wait for positive clock edge If (STOP) RUNNING = 0 Else if (START) RUNNING = 1 RUNNING End if START = 0 START STOP = 0 CNT = CNT - 1 CNT = = 0 CNT = = 0 CNT = CNT - 1...
Page 591: Letimer Clock Frequency
...the world's most energy friendly microcontrollers Figure 23.5. LETIMER Double Repeat State Machine Wait for positive clock edge If (STOP) RUNNING = 0 Else if (START) RUNNING = 1 RUNNING End if START = 0 START STOP = 0 CNT = CNT - 1 CNT = = 0 CNT = = 0 CNT = CNT - 1...
Page 592 ...the world's most energy friendly microcontrollers continue running if triggered while it is running, so the multiple-triggering will only have an effect if you try to disable the RTC when it is being triggered. 23.3.3.5 Debug If DEBUGRUN in LETIMERn_CTRL is cleared, the LETIMER automatically stops counting when the CPU is halted during a debug session, and resumes operation when the CPU continues.
Page 593 ...the world's most energy friendly microcontrollers Some simple waveforms generated with the different output modes are shown in Figure 23.6 (p. 593) . For the example, REPMODE in LETIMERn_CTRL has been cleared, COMP0TOP also in LETIMERn_CTRL has been set and LETIMERn_COMP0 has been written to 3. As seen in the figure, LETIMERn_COMP0 now decides the length of the signal periods.
Page 594 ...the world's most energy friendly microcontrollers Figure 23.8. LETIMER Dual Output UFOA0 = 10 UFOA1 = 10 REP0 = 2 REP0 = 2 REP1 = 7 REP0 = 3 REP1 = 3 START START START LETn_O0 LETn_O1 23.3.5 PRS Output The LETIMER outputs can be routed out onto the PRS system.
Page 595 ...the world's most energy friendly microcontrollers 23.3.6.1 Triggered Output Generation Example 23.1. LETIMER Triggered Output Generation If both LETIMERn_CNT and LETIMERn_REP0 are 0 in buffered mode, and COMP0TOP and BUFTOP in LETIMERn_CTRL are set, the values of LETIMERn_COMP1 and LETIMERn_REP1 are loaded into LETIMERn_CNT and LETIMERn_REP0 respectively when the timer is started.
Page 596 ...the world's most energy friendly microcontrollers 23.3.6.2 Continuous Output Generation Example 23.2. LETIMER Continuous Output Generation In some scenarios, it might be desired to make LETIMER generate a continuous waveform. Very simple constant waveforms can be generated without the repeat counter as shown in Figure 23.6 (p. 593) , but to generate changing waveforms, using the repeat counter and buffer registers can prove advantageous.
Page 597 ...the world's most energy friendly microcontrollers Multiple LETIMER cycles are required to write a value to the LETIMER registers. The example in Figure 23.10 (p. 596) assumes that writes are done in advance so they arrive in the LETIMER as described in the figure. Figure 23.11 (p.
Page 598 ...the world's most energy friendly microcontrollers 23.3.7 Using the LETIMER in EM3 The LETIMER can be enabled all the way down to EM3 by using the ULFRCO as clock source. This is done by clearing CMU_LFCLKSEL_LFA and setting CMU_LFCLKSEL_LFAE to 1. This will make the RTC use the internal 1 kHz ultra low frequency RC oscillator (ULFRCO), consuming very little energy.
Page 599: Register Map
...the world's most energy friendly microcontrollers 23.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LETIMERn_CTRL Control Register 0x004 LETIMERn_CMD Command Register 0x008 LETIMERn_STATUS Status Register 0x00C LETIMERn_CNT Counter Value Register 0x010 LETIMERn_COMP0 Compare Value Register 0...
Page 600 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description A compare match on RTC compare channel 1 starts the LETIMER if the LETIMER is not already started RTCC0TEN RTC Compare 0 Trigger Enable Allows the LETIMER to be started on a compare match on RTC compare channel 0. Value Description LETIMER is not affected by RTC compare channel 0...
Page 601 ...the world's most energy friendly microcontrollers 23.5.2 LETIMERn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CTO1 Clear Toggle Output 1 Set to drive toggle output 1 to its idle value...
Page 602 ...the world's most energy friendly microcontrollers 23.5.4 LETIMERn_CNT - Counter Value Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0x0000 Counter Value...
Page 603 ...the world's most energy friendly microcontrollers Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 COMP1 0x0000 Compare Value 1 Compare and optionally buffered top value for LETIMER 23.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg)
Page 604 ...the world's most energy friendly microcontrollers Name Reset Access Description REP1 0x00 Repeat Counter 1 Optional repeat counter or buffer for REP0 23.5.9 LETIMERn_IF - Interrupt Flag Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 605 ...the world's most energy friendly microcontrollers Name Reset Access Description COMP1 Set Compare Match 1 Interrupt Flag Write to 1 to set the COMP1 interrupt flag. COMP0 Set Compare Match 0 Interrupt Flag Write to 1 to set the COMP0 interrupt flag. 23.5.11 LETIMERn_IFC - Interrupt Flag Clear Register Offset Bit Position...
Page 606 ...the world's most energy friendly microcontrollers Name Reset Access Description Underflow Interrupt Enable Set to enable interrupt on the UF interrupt flag. COMP1 Compare Match 1 Interrupt Enable Set to enable interrupt on the COMP1 interrupt flag. COMP0 Compare Match 0 Interrupt Enable Set to enable interrupt on the COMP0 interrupt flag.
Page 607 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when the value written to COMP0 is being synchronized. CMD Register Busy Set when the value written to CMD is being synchronized. CTRL CTRL Register Busy Set when the value written to CTRL is being synchronized. 23.5.15 LETIMERn_ROUTE - I/O Routing Register Offset Bit Position...
Page 608: Pcnt - Pulse Counter
...the world's most energy friendly microcontrollers 24 PCNT - Pulse Counter Quick Facts What? 0 1 2 3 The Pulse Counter (PCNT) decodes incoming pulses. The module has a quadrature mode which may be used to decode the speed and direction of a mechanical shaft.
Page 609 ...the world's most energy friendly microcontrollers Figure 24.1. PCNT Overview CMU (conseptual) LFACLK Clock switch PCNT S0PRS Input Peripheral bus OVR_SINGLE Edge Pulse Width Inverter detector Filter TOPB EXTCLK_SINGLE EXTCLK_QUAD Quadrature Inverter decoder S1PRS Input 24.3.1 Pulse Counter Modes The pulse counter can operate in single input oversampling mode (OVSSINGLE), externally clocked single input counter mode (EXTCLKSINGLE) and externally clocked quadrature decoder mode (EXTCLKQUAD).
Page 610 ...the world's most energy friendly microcontrollers The digital pulse width filter is not available in this mode. The analog de-glitch filter in the GPIO pads is capable of removing some unwanted noise. However, this mode may be susceptible to spikes and unintended pulses from devices such as mechanical switches, and is therefore most suited to take input from electronic sensors etc.
Page 611: Absolute Position With Hysteresis And Even Top Value
...the world's most energy friendly microcontrollers The direction of the quadrature code and control of the counter is generated by the simple binary function outlined by Table 24.1 (p. 611) . Note that this function also filters some invalid inputs that may occur when the shaft changes direction or temporarily toggles direction.
Page 612 ...the world's most energy friendly microcontrollers As the auxiliary counter, the main counter can be configured to count only on certain events. This is done through CNTEV in PCNTn_CTRL, and it is possible like for the auxiliary counter, to make the main counter count on only up and down events.
Page 613 ...the world's most energy friendly microcontrollers In EXTCLKQUAD mode, the EDGE bit in PCNTn_CTRL inverts the direction of the counter (which is automatically detected). Note The EDGE bit in PCNTn_CTRL has no effect in EXTCLKSINGLE mode. 24.3.8 PRS S0IN and S1IN Input It is possible to receive input from PRS on both SOIN and S1IN by setting S0PRSEN or S1PRSEN in PCNTn_INPUT.
Page 614: Register Map
...the world's most energy friendly microcontrollers 24.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PCNTn_CTRL Control Register 0x004 PCNTn_CMD Command Register 0x008 PCNTn_STATUS Status Register 0x00C PCNTn_CNT Counter Value Register 0x010 PCNTn_TOP Top Value Register...
Page 615 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description BOTH Counts up on up-count and down on down-count events. Only counts up on up-count events. DOWN Only counts down on down-count events. NONE Never counts. S1CDIR Count direction determined by S1 S1 gives the direction of counting when in the OVSSINGLE or EXTCLKSINGLE modes.
Page 616 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LTOPBIM Load TOPB Immediately This bit has no effect since TOPB is not buffered and it is loaded directly into TOP. LCNTIM Load CNT Immediately Load PCNTn_TOP into PCNTn_CNT on the next counter clock cycle.
Page 617 ...the world's most energy friendly microcontrollers 24.5.5 PCNTn_TOP - Top Value Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0x00FF Counter Top Value...
Page 618 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) AUXOF Overflow Interrupt Read Flag Set when an Auxiliary CNT overflow occurs DIRCNG Direction Change Detect Interrupt Flag Set when the count direction changes.
Page 619 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to clear the auxiliary overflow interrupt flag DIRCNG Direction Change Detect Interrupt Clear Write to 1 to clear the direction change detect interrupt flag Overflow Interrupt Clear Write to 1 to clear the overflow interrupt flag Underflow Interrupt Clear Write to 1 to clear the underflow interrupt flag...
Page 620 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description LOC1 Location 1 LOC2 Location 2 LOC3 Location 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 24.5.12 PCNTn_FREEZE - Freeze Register Offset Bit Position...
Page 621 ...the world's most energy friendly microcontrollers 24.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 AUXCNT 0x0000...
Page 622 ...the world's most energy friendly microcontrollers Name Reset Access Description S0PRSEN S0IN PRS Enable When set, the PRS channel is selected as input to S0IN. S0PRSSEL S0IN PRS Channel Select Select PRS channel as input to S0IN. Value Mode Description PRSCH0 PRS Channel 0 selected.
Page 623: Lesense - Low Energy Sensor Interface
...the world's most energy friendly microcontrollers 25 LESENSE - Low Energy Sensor Interface Quick Facts What? LESENSE is a low energy sensor interface capable of autonomously collecting and 0 1 2 3 processing data from multiple sensors even when in EM2. Flexible configuration makes LESENSE a versatile sensor interface compatible with a wide range of sensors and measurement schemes.
Page 624: Functional Description
...the world's most energy friendly microcontrollers 25.3 Functional description LESENSE is a module capable of controlling on-chip peripherals in order to perform monitoring of different sensors with little or no CPU intervention. LESENSE uses the analog comparators, ACMP, for measurement of sensor signals. LESENSE can also control the DAC to generate accurate reference voltages.
Page 625 ...the world's most energy friendly microcontrollers the channel configuration registers, CHx_TIMING, CHx_INTERACT, and CHx_EVAL, throughout this chapter. By default, the channel configuration registers are directly mapped to the channel number. Configuring SCANCONF in CTRL makes it possible to alter this mapping. Configuring SCANCONF to INVMAP will make channels 0-7 use the channel configuration registers for channels 8-15, and vice versa.
Page 626: Scan Frequency
...the world's most energy friendly microcontrollers ONESHOT, a single scan will be made when START in CMD is set. To start a new scan on a PRS event, set START in CMD, set SCANMODE to PRS and configure PRS channel in PRSSEL. The PRS start signal needs to be active for at least one LFACLK cycle to make sure LESENSE is able LESENSE...
Page 627 ...the world's most energy friendly microcontrollers 25.3.4 Sensor interaction Many sensor types require some type of excitation in order to work. LESENSE can generate a variety of sensor stimuli, both on the same pin as the measurement is to be made on, and on alternative pins. By default, excitation is performed on the pin associated with the channel, i.e.
Page 628 ...the world's most energy friendly microcontrollers Figure 25.4 (p. 628) illustrates the sequencing of the pin associated with the active channel and its alternative excite pin. Figure 25.4. Pin sequencing LFACLK LESENSE EXCITE Idle phase Ex cite phase Measure phase Idle phase Channel pin IDLECONF...
Page 629 ...the world's most energy friendly microcontrollers Figure 25.5. Scan result and interrupt generation CHx _EVAL_SCANRESINV ACMP ACMP sam ple SCANRES[x ] NEGEDGE COUNTER > = COMPTHRES POSEDGE interrupt LESENSE flag COUNTER counter LEVEL CHx _INTERACT_SAMPLE SENSORSTATE NONE COUNTER < COMPTHRES LESS CHx _EVAL_COMP CHx _INTERACT_SETIF...
Page 630 ...the world's most energy friendly microcontrollers mask out one or more sensors using the MASK bit field. The state of a masked sensor is interpreted as don't care. Upon a state transition, LESENSE can generate a pulse on one or more of the decoder PRS channels. Which channel to generate a pulse on is configured in the PRSACT bit field.
Page 631 ...the world's most energy friendly microcontrollers Figure 25.7. Decoder state transition evaluation STATE TCONF Generate PRS SENSORSTATE & ~MASK signals and set COMP & ~MASK interrupt flag NEXTSTATE Generate PRS SENSORSTATE & ~MASK signals and set COMP & ~MASK interrupt flag NEXTSTATE CHAIN i+ 1...
Page 632 ...the world's most energy friendly microcontrollers Figure 25.8. Decoder hysteresis State 0 A transition: Transition defined in TCONFA B transition: Transition defined in TCONFB 1: B transition, no hysteresis State 1 2: A transition, hysteresis 4: A transition, hysteresis 3: B transition, hysteresis State 2 5: A transition, no hysteresis State 3...
Page 633: Bias Configuration
...the world's most energy friendly microcontrollers Figure 25.9. Circular result buffer BUF0_DATA CH3 result BUF1_DATA CH5 result LESENSE BUF2_DATA CH9 result BUF3_DATA SCANRES PTR_RD BUFDATA PTR_WR BUF12_DATA CH3 result BUF13_DATA CH5 result BUF14_DATA CH9 result BUF15_DATA SCANRES The right hand side of Figure 25.9 (p. 633) illustrates how the result buffer would be filled when channels 3,5, and 9 are enabled and have STRSAMPLE in CHx_EVAL set, in addition to STRSCANRES in CTRL.
Page 634 ...the world's most energy friendly microcontrollers ACMP1MODE bit-fields in PERCTRL, LESENSE will take control of the positive input mux and the Vdd scaling factor (VDDLEVEL) for ACMP0 and ACMP1. The remaining configuration of the analog comparators are done in the ACMP register interface. It is recommended to set the MUXEN bit in ACMPn_CTRL for the ACMPs used by LESENSE.
Page 635 ...the world's most energy friendly microcontrollers Figure 25.10. Capacitive sense setup EFM32 ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 The following steps show how to configure LESENSE to scan through the four buttons 100 times per second, issuing an interrupt if one of them is pressed. 1.
Page 636 ...the world's most energy friendly microcontrollers exceeds a certain level. These pulses are counted using an asynchronous counter and compared with the threshold in COMPTHRES in the CHx_EVAL register. If the number of pulses exceeds the threshold level, the sensor is said to be active, otherwise it is inactive. Figure 25.12 (p. 636) illustrates how the output pulses from the ACMP correspond to damping of the oscillations.
Page 637 ...the world's most energy friendly microcontrollers Figure 25.13. FSM example 1 Sensor value State Index 010 110 000 100 To set up the decoder to decode rotation using the encoding scheme seen in Figure 25.13 (p. 637) , configure the following LESENSE registers: 1.
Page 638: Lesense Decoder Configuration
...the world's most energy friendly microcontrollers 1. Configure STx_TCONFA and STx_TCONFB as described in Table 25.4 (p. 638) . Table 25.4. LESENSE decoder configuration Register NEXTSTATE COMP MASK CHAIN ST0_TCONFA 0b1000 0b0111 ST0_TCONFB 0b0001 0b1000 ST1_TCONFA 0b0010 0b1000 ST1_TCONFB 0b0010 0b1000 ST2_TCONFA 0b1000...
Page 639: Register Map
...the world's most energy friendly microcontrollers 25.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LESENSE_CTRL Control Register 0x004 LESENSE_TIMCTRL Timing Control Register 0x008 LESENSE_PERCTRL Peripheral Control Register 0x00C LESENSE_DECCTRL Decoder control Register 0x010 LESENSE_BIASCTRL...
Page 640: Register Description
...the world's most energy friendly microcontrollers Offset Name Type Description 0x3B8 LESENSE_CH15_EVAL Scan configuration 25.5 Register Description 25.5.1 LESENSE_CTRL - Control Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x000 Reset Access...
Page 641 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description ALTEX Alternative excitation is mapped to the LES_ALTEX pins. ACMP Alternative excitation is mapped to the pins of the other ACMP. ACMP1INV Invert analog comparator 1 output ACMP0INV Invert analog comparator 0 output Reserved...
Page 642 ...the world's most energy friendly microcontrollers Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:22 STARTDLY Start delay configuration Delay sensor interaction STARTDELAY LFACLK cycles for each channel LESENSE...
Page 643 ...the world's most energy friendly microcontrollers 25.5.3 LESENSE_PERCTRL - Peripheral Control Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 644 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DAC CH1 output to pin enabled, output to ADC and ACMP disabled ADCACMP DAC CH1 output to pin disabled, output to ADC and ACMP enabled PINADCACMP DAC CH1 output to pin, ADC, and ACMP enabled. DACCH0OUT DAC channel 0 output mode Value...
Page 645 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 25:22 PRSSEL3 Select PRS input for bit 3 of the LESENSE decoder Value Mode Description...
Page 646 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PRSCH3 PRS Channel 3 selected as input PRSCH4 PRS Channel 4 selected as input PRSCH5 PRS Channel 5 selected as input PRSCH6 PRS Channel 6 selected as input PRSCH7 PRS Channel 7 selected as input PRSCH8...
Page 647 ...the world's most energy friendly microcontrollers Name Reset Access Description BIASMODE Select bias mode Value Mode Description DUTYCYCLE Bias module duty cycled between low power and high accuracy mode HIGHACC Bias module always in high accuracy mode DONTTOUCH Bias module not affected by LESENSE 25.5.6 LESENSE_CMD - Command Register Offset Bit Position...
Page 648 ...the world's most energy friendly microcontrollers Name Reset Access Description Set bit X to enable channel X 25.5.8 LESENSE_SCANRES - Scan result register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x01C Reset Access...
Page 649 ...the world's most energy friendly microcontrollers Name Reset Access Description BUFDATAV Result data valid Set when data is available in the result buffer. Cleared when the buffer is empty. 25.5.10 LESENSE_PTR - Result buffer pointers (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x024...
Page 650 ...the world's most energy friendly microcontrollers Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CURCH Shows the index of the current channel 25.5.13 LESENSE_DECSTATE - Current decoder state (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 651 ...the world's most energy friendly microcontrollers 25.5.15 LESENSE_IDLECONF - GPIO Idle phase configuration (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:30 CH15 Channel 15 idle phase configuration Value...
Page 652 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description CH10 output is low in idle phase 19:18 Channel 9 idle phase configuration Value Mode Description DISABLE CH9 output is disabled in idle phase HIGH CH9 output is high in idle phase CH9 output is low in idle phase 17:16 Channel 8 idle phase configuration...
Page 653 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DISABLE CH2 output is disabled in idle phase HIGH CH2 output is high in idle phase CH2 output is low in idle phase DACCH0 CH2 output is connected to DAC CH0 output in idle phase Channel 1 idle phase configuration Value Mode...
Page 654 ...the world's most energy friendly microcontrollers Name Reset Access Description AEX1 ALTEX1 always excite enable AEX0 ALTEX0 always excite enable 15:14 IDLECONF7 ALTEX7 idle phase configuration Value Mode Description DISABLE ALTEX7 output is disabled in idle phase HIGH ALTEX7 output is high in idle phase ALTEX7 output is low in idle phase 13:12 IDLECONF6...
Page 655 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DISABLE ALTEX0 output is disabled in idle phase HIGH ALTEX0 output is high in idle phase ALTEX0 output is low in idle phase 25.5.17 LESENSE_IF - Interrupt Flag Register Offset Bit Position 0x040...
Page 656 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when channel 8 triggers Set when channel 7 triggers Set when channel 6 triggers Set when channel 5 triggers Set when channel 4 triggers Set when channel 3 triggers Set when channel 2 triggers Set when channel 1 triggers Set when channel 0 triggers...
Page 657 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to clear SCANCOMPLETE interrupt flag CH15 Write to 1 to clear CH15 interrupt flag CH14 Write to 1 to clear CH14 interrupt flag CH13 Write to 1 to clear CH13 interrupt flag CH12 Write to 1 to clear CH12 interrupt flag CH11...
Page 658 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CNTOF Write to 1 to set the CNTOF interrupt flag BUFOF Write to 1 to set the BUFOF interrupt flag BUFLEVEL...
Page 659 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to set the CH0 interrupt flag 25.5.20 LESENSE_IEN - Interrupt Enable Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CNTOF Set to enable interrupt on the CNTOF interrupt flag BUFOF...
Page 660 ...the world's most energy friendly microcontrollers Name Reset Access Description Set to enable interrupt on the CH8 interrupt flag Set to enable interrupt on the CH7 interrupt flag Set to enable interrupt on the CH6 interrupt flag Set to enable interrupt on the CH5 interrupt flag Set to enable interrupt on the CH4 interrupt flag Set to enable interrupt on the CH3 interrupt flag Set to enable interrupt on the CH2 interrupt flag...
Page 661 ...the world's most energy friendly microcontrollers Name Reset Access Description ROUTE LESENSE_ROUTE Register Busy Set when the value written to LESENSE_ROUTE is being synchronized. ALTEXCONF LESENSE_ALTEXCONF Register Busy Set when the value written to LESENSE_ALTEXCONF is being synchronized. IDLECONF LESENSE_IDLECONF Register Busy Set when the value written to LESENSE_IDLECONF is being synchronized.
Page 662 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ALTEX7PEN ALTEX7 Pin Enable ALTEX6PEN ALTEX6 Pin Enable ALTEX5PEN ALTEX5 Pin Enable ALTEX4PEN ALTEX4 Pin Enable ALTEX3PEN...
Page 663 ...the world's most energy friendly microcontrollers Name Reset Access Description CH1PEN CH0 Pin Enable CH0PEN CH0 Pin Enable 25.5.23 LESENSE_POWERDOWN - LESENSE RAM power-down register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x058...
Page 664 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 14:12 PRSACT Configure transition action Configure which action to perform when sensor state equals COMP DECCTRL_PRSCNT = 0 Mode Value...
Page 665 ...the world's most energy friendly microcontrollers Name Reset Access Description DECCTRL_PRSCNT = 0 Mode Value Description NONE No PRS pulses generated PRS0 Generate pulse on PRS0 PRS1 Generate pulse on PRS1 PRS01 Generate pulse on PRS0 and PRS1 PRS2 Generate pulse on PRS2 PRS02 Generate pulse on PRS0 and PRS2 PRS12...
Page 666 ...the world's most energy friendly microcontrollers Offset Bit Position 0x2C0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19:13 MEASUREDLY 0xXX Set measure delay Configure measure delay.
Page 667 ...the world's most energy friendly microcontrollers Name Reset Access Description 16:15 EXMODE Set GPIO mode GPIO mode for the excitation phase of the scan sequence. Note that DACOUT is only available on channels 0, 1, 2, 3, 12, 13, 14, and 15.
Page 668 ...the world's most energy friendly microcontrollers Name Reset Access Description CH_INTERACT_SAMPLE COUNTER Mode Value Description LESS Comparison evaluates to 1 if counter value is less than COMPTHRES. Comparison evaluates to 1 if counter value is greater than, or equal to COMPTHRES. CH_INTERACT_SAMPLE ACMP LESS...
Page 669: Acmp - Analog Comparator
...the world's most energy friendly microcontrollers 26 ACMP - Analog Comparator Quick Facts What? The ACMP (Analog Comparator) compares two analog signals and returns a digital value telling which is greater. 0 1 2 3 Why? Applications often do not need to know the exact value of an analog signal, only if it has passed a certain threshold.
Page 670: Functional Description
...the world's most energy friendly microcontrollers • Configurable inversion of comparator output • Configurable output when inactive • Comparator output direct on PRS • Comparator output on GPIO through alternate functionality • Output inversion available 26.3 Functional Description An overview of the ACMP is shown in Figure 26.1 (p. 670) . Figure 26.1.
Page 671: Bias Configuration
...the world's most energy friendly microcontrollers One should wait until the warm-up period is over before entering EM2 or EM3, otherwise no comparator interrupts will be detected. EM1 can still be entered during warm-up. After the warm-up period is completed, interrupts will be detected in EM2 and EM3. 26.3.2 Response Time There is a delay from when the actual input voltage changes polarity, to when the output toggles.
Page 672 ...the world's most energy friendly microcontrollers Figure 26.2. 20 mV Hysteresis Selected + 20m V Tim e - 20m V ACMPOUT without hysteresis ACMPOUT with hysteresis 26.3.4 Input Selection The POSSEL and NEGSEL fields in ACMPn_INPUTSEL controls which signals are connected to the two inputs of the comparator.
Page 673 ...the world's most energy friendly microcontrollers Figure 26.3. Capacitive Sensing Set-up Buttons POSSEL DD_SCALED 26.3.6 Interrupts and PRS Output The analog comparator includes an edge triggered interrupt flag (EDGE in ACMPn_IF). If either IRISE and/or IFALL in ACMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output, respectively.
Page 674: Register Map
...the world's most energy friendly microcontrollers 26.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ACMPn_CTRL Control Register 0x004 ACMPn_INPUTSEL Input Selection Register 0x008 ACMPn_STATUS Status Register 0x00C ACMPn_IEN Interrupt Enable Register 0x010 ACMPn_IF Interrupt Flag Register...
Page 675 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 4CYCLES 4 HFPERCLK cycles. 8CYCLES 8 HFPERCLK cycles. 16CYCLES 16 HFPERCLK cycles. 32CYCLES 32 HFPERCLK cycles. 64CYCLES 64 HFPERCLK cycles. 128CYCLES 128 HFPERCLK cycles. 256CYCLES 256 HFPERCLK cycles. 512CYCLES 512 HFPERCLK cycles.
Page 676 ...the world's most energy friendly microcontrollers Name Reset Access Description 29:28 CSRESSEL Capacitive Sense Mode Internal Resistor Select These bits select the resistance value for the internal capacitive sense resistor. Resulting actual resistor values are given in the device datasheets. Value Mode Description...
Page 677 ...the world's most energy friendly microcontrollers 26.5.3 ACMPn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ACMPOUT Analog Comparator Output Analog comparator output value.
Page 678 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) WARMUP Warm-up Interrupt Flag Indicates that the analog comparator warm-up period is finished. EDGE Edge Triggered Interrupt Flag Indicates that there has been a rising or falling edge on the analog comparator output.
Page 679 ...the world's most energy friendly microcontrollers 26.5.8 ACMPn_ROUTE - I/O Routing Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 LOCATION I/O Location...
Page 680: Vcmp - Voltage Comparator
...the world's most energy friendly microcontrollers 27 VCMP - Voltage Comparator Quick Facts What? 0 1 2 3 The Voltage Supply Comparator (VCMP) monitors the input voltage supply and generates software interrupts on events using as little as 100 nA. Why? The VCMP can be used for simple power supply monitoring, e.g.
Page 681: Functional Description
...the world's most energy friendly microcontrollers 27.3 Functional Description An overview of the VCMP is shown in Figure 27.1 (p. 681) . Figure 27.1. VCMP Overview Warm up interrupt Warm - up TRIGLEVEL VCMPACT counter Edge interrupt Scaler VCMPOUT INACTVAL BIASPROG HALFBIAS LPREF...
Page 682: Dd Trigger Level
...the world's most energy friendly microcontrollers BIAS Bias Current (µA) HALFBIAS=0 HALFBIAS=1 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 0b1011 0b1100 0b1101 0b1110 0b1111 27.3.3 Hysteresis In the voltage supply comparator, hysteresis can be enabled by setting HYSTEN in VCMP_CTRL. When HYSTEN is set, the digital output will not toggle until the positive input voltage is at least 20mV above or below the negative input voltage.
Page 683 ...the world's most energy friendly microcontrollers 27.3.5 Interrupts and PRS Output The VCMP includes an edge triggered interrupt flag (EDGE in VCMP_IF). If either IRISE and/or IFALL in VCMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output respectively.
Page 684: Register Map
...the world's most energy friendly microcontrollers 27.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 VCMP_CTRL Control Register 0x004 VCMP_INPUTSEL Input Selection Register 0x008 VCMP_STATUS Status Register 0x00C VCMP_IEN Interrupt Enable Register 0x010 VCMP_IF Interrupt Flag Register...
Page 685 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 512CYCLES 512 HFPERCLK cycles Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) HYSTEN Hysteresis Enable Enable hysteresis. Value Description No hysteresis...
Page 686 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) VCMPOUT Voltage Supply Comparator Output Voltage supply comparator output value VCMPACT Voltage Supply Comparator Active Voltage supply comparator active status.
Page 687 ...the world's most energy friendly microcontrollers 27.5.6 VCMP_IFS - Interrupt Flag Set Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) WARMUP Warm-up Interrupt Flag Set Write to 1 to set warm-up finished interrupt flag...
Page 688: Adc - Analog To Digital Converter
...the world's most energy friendly microcontrollers 28 ADC - Analog to Digital Converter Quick Facts What? The ADC is used to convert analog signals into a digital representation and features 8 external input channels 0 1 2 3 Why? In many applications there is a need to measure analog signals and record them in a digital representation, without exhausting your energy source.
Page 689: Functional Description
...the world's most energy friendly microcontrollers • Programmable scan sequence • Up to 8 configurable samples in scan sequence • Mask to select which pins are included in the sequence • Triggered by software or PRS input • One shot or repetitive mode •...
Page 690: Adc Overview
...the world's most energy friendly microcontrollers Figure 28.1. ADC Overview ADCn_CTRL ADCn_SINGLEDATA ADCn_CMD ADCn_SCANDATA ADCn_SINGLECTRL ADCn_STATUS ADCn_SCANCTRL Oversam pling filter Sequencer HFPERCLK ADC_CLK ADCn Prescaler Result buffer ADCn_CH0 ADCn_CH1 Control ADCn_CH2 ADCn_CH3 ADCn_CH4 ADCn_CH5 ADCn_CH6 ADCn_CH7 Tem p DAC0/ OPA0 DAC1/ OPA1 1.25 V 2.5 V...
Page 691: Adc Conversion Timing
...the world's most energy friendly microcontrollers Figure 28.2. ADC Conversion Timing HFPERCLK ADCn Prescaled clock (4x ) SINGLEAT/ ADC action Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCANAT...
Page 692 ...the world's most energy friendly microcontrollers Figure 28.3. ADC Analog Power Consumption With Different WARMUPMODE Settings Bandgap reference warm - up ADC warm - up ADC conversion ADC enabled Conversion trigger Conversion trigger Power NORMAL 5 µs Tim e 1 µs 1 µs Power KEEPSCANREFWARM 5 µs...
Page 693: Adc Temperature Measurement
...the world's most energy friendly microcontrollers Figure 28.4. ADC RC Input Filter Configuration Input 28.3.4.2 Temperature Measurement The ADC includes an internal temperature sensor. This sensor is characterized during production and the temperature readout from the ADC at production temperature, ADC0_TEMP_0_READ_1V25, is given in the Device Information (DI) page.
Page 694 ...the world's most energy friendly microcontrollers bitfields scale the current of ADC bandgap reference, and the COMPBIAS bits provide an additional bias programming for the ADC comparator as illustrated in Figure 28.5 (p. 694) . The electrical characteristics given in the datasheet require the bias configuration to be set to the default values, where no other bias values are given.
Page 695: Adc Conversion Tailgating
...the world's most energy friendly microcontrollers single sample just before a scan trigger can delay the start of the scan sequence, thus causing jitter in sample rate. To solve this, conversion tailgating can be chosen by setting TAILGATE in ADCn_CTRL. When this bit is set, any triggered single samples will wait for the next scan sequence to finish before activating (see Figure 28.6 (p.
Page 696 ...the world's most energy friendly microcontrollers Table 28.2. ADC Differential Conversion Results Input/Reference Binary Hex value 011111111111 0.25 001111111111 1/2048 000000000001 000000000000 -1/2048 111111111111 -0.25 101111111111 -0.5 100000000000 28.3.7.6 Resolution The ADC gives out 12-bit results, by default. However, if full 12-bit resolution is not needed, it is possible to speed up the conversion by selecting a lower resolution (N = 6 or 8 bits).
Page 697 ...the world's most energy friendly microcontrollers 28.3.7.8 Adjustment By default, all results are right adjusted, with the LSB of the result in bit position 0 (zero). In differential mode the signed bit is extended up to bit 31, but in single ended mode the bits above the result are read as 0.
Page 698: Calibration Register Effect
...the world's most energy friendly microcontrollers The effects of changing the calibration register values are given in Table 28.5 (p. 698) . Step by step calibration procedures for offset and gain are given in Section 28.3.10.1 (p. 698) and Section 28.3.10.2 (p. 698) . Table 28.5.
Page 699: Register Map
...the world's most energy friendly microcontrollers 28.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ADCn_CTRL Control Register 0x004 ADCn_CMD Command Register 0x008 ADCn_STATUS Status Register 0x00C ADCn_SINGLECTRL Single Sample Control Register 0x010 ADCn_SCANCTRL Scan Control Register...
Page 700 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description X1024 1024 samples for each conversion result X2048 2048 samples for each conversion result X4096 4096 samples for each conversion result 23:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:16 TIMEBASE 0x1F...
Page 701 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANSTOP Scan Sequence Stop Write a 1 to stop scan sequence. SCANSTART Scan Sequence Start Write a 1 to start scan sequence.
Page 702 ...the world's most energy friendly microcontrollers Name Reset Access Description Reference selected for scan mode is warmed up. SINGLEREFWARM Single Reference Warmed Up Reference selected for single mode is warmed up. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANACT Scan Conversion Active Scan sequence is active or has pending conversions.
Page 703 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 16CYCLES 16 ADC_CLK cycles acquisition time for single sample 32CYCLES 32 ADC_CLK cycles acquisition time for single sample 64CYCLES 64 ADC_CLK cycles acquisition time for single sample 128CYCLES 128 ADC_CLK cycles acquisition time for single sample 256CYCLES...
Page 704 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description Oversampling enabled. Oversampling rate is set in OVSRSEL Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Single Sample Result Adjustment Select single sample result adjustment.
Page 705 ...the world's most energy friendly microcontrollers Name Reset Access Description Enabled/disable PRS trigger of scan sequence. Value Description Scan sequence is not triggered by PRS input Scan sequence is triggered by PRS input selected by PRSSEL 23:20 Scan Sample Acquisition Time Select the acquisition time for scan samples.
Page 706 ...the world's most energy friendly microcontrollers Name Reset Access Description Select scan sequence conversion resolution. Value Mode Description 12BIT 12-bit resolution 8BIT 8-bit resolution 6BIT 6-bit resolution Oversampling enabled. Oversampling rate is set in OVSRSEL Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Scan Sequence Result Adjustment Select scan sequence result adjustment.
Page 707 ...the world's most energy friendly microcontrollers 28.5.7 ADCn_IF - Interrupt Flag Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANOF Scan Result Overflow Interrupt Flag Indicates scan result overflow when this bit is set.
Page 708 ...the world's most energy friendly microcontrollers 28.5.9 ADCn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANOF Scan Result Overflow Interrupt Flag Clear Write to 1 to clear scan result overflow interrupt flag.
Page 709 ...the world's most energy friendly microcontrollers 28.5.11 ADCn_SCANDATA - Scan Conversion Result Data Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:0 DATA 0x00000000 Scan Conversion Result Data The register holds the results from the last scan conversion. Reading this field clears the SCANDV bit in the ADCn_STATUS register. 28.5.12 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register Offset...
Page 710 ...the world's most energy friendly microcontrollers 28.5.13 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:0 DATAP 0x00000000 Scan Conversion Result Data Peek The register holds the results from the last scan conversion. Reading this field will not clear SCANDV in ADCn_STATUS or single DMA request.
Page 711 ...the world's most energy friendly microcontrollers Name Reset Access Description This register contains the offset calibration value used with single conversions. This field is set to the production offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is encoded as a signed 2's complement number.
Page 712: Dac - Digital To Analog Converter
...the world's most energy friendly microcontrollers 29 DAC - Digital to Analog Converter Quick Facts What? The DAC is designed for low energy consumption, but can also provide very good performance. It can convert digital values 0 1 2 3 to analog signals at up to 500 kilo samples/ second and with 12-bit accuracy.
Page 713: Functional Description
...the world's most energy friendly microcontrollers • Output to ADC • Sine generation mode • Optional high strength line driver 29.3 Functional Description An overview of the DAC module is shown in Figure 29.1 (p. 713) . Figure 29.1. DAC Overview DACn_OUT0 Ch 0 CH0DATA...
Page 714: Dac Clock Prescaling
...the world's most energy friendly microcontrollers a combined data register, DACn_COMBDATA, where the data values for both channels can be written simultaneously. Writing to this register will start all enabled channels. If the PRSEN bit in DACn_CHxCTRL is set, a DAC conversion on channel x will not be started by data write, but when a positive one HFPERCLK cycle pulse is received on the PRS input selected by PRSSEL in DACn_CHxCTRL.
Page 715: Dac Single Ended Output Voltage
...the world's most energy friendly microcontrollers Figure 29.2. DAC Bias Programming Reference BIASPROG Current HALFBIAS Internal DAC output bandgap buffer reference The minimum value of the BIASPROG bit-field of the DACn_BIASPROG register (i.e. BIASPROG=0b0000) represents the minimum bias current. Similarly BIASPROG=0b1111 represents the maximum bias current.
Page 716: Dac Sine Mode
...the world's most energy friendly microcontrollers table. The sine signal is controlled by the PRS line selected by CH0PRSSEL in DACn_CH0CTRL. When the PRS line is low, a voltage of Vref/2 will be produced. When the line is high, a sine wave will be produced.
Page 717 ...the world's most energy friendly microcontrollers The DAC channels can also drive an alternative output network, which is described in the Opamp chapter in Section 30.3.1.2 (p. 735) . To enable this network, OUTMODE must be configured to ADC in DACn_CTRL. The actual output network can be configred by configuring DACn_OPAxMUX registers. 29.3.9 Calibration The DAC contains a calibration register, DACn_CAL, where calibration values for both offset and gain correction can be written.
Page 718: Register Map
...the world's most energy friendly microcontrollers 29.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DACn_CTRL Control Register 0x004 DACn_STATUS Status Register 0x008 DACn_CH0CTRL Channel 0 Control Register 0x00C DACn_CH1CTRL Channel 1 Control Register 0x010 DACn_IEN...
Page 719 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 64CYCLES All channels with enabled refresh are refreshed every 64 prescaled cycles Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:16 PRESC Prescaler Setting...
Page 720 ...the world's most energy friendly microcontrollers 29.5.2 DACn_STATUS - Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH1DV Channel 1 Data Valid This bit is set high when CH1DATA is written and is set low when CH1DATA is used in conversion.
Page 721 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description Channel 0 is triggered by PRS input REFREN Channel 0 Automatic Refresh Enable Set to enable automatic refresh of channel 0. Refresh period is set by REFRSEL in DACn_CTRL. Value Description Channel 0 is not refreshed automatically...
Page 722 ...the world's most energy friendly microcontrollers Name Reset Access Description Channel 1 Enable Enable/disable channel 1. 29.5.5 DACn_IEN - Interrupt Enable Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH1UF Channel 1 Conversion Data Underflow Interrupt Enable Enable/disable channel 1 data underflow interrupt.
Page 723 ...the world's most energy friendly microcontrollers Name Reset Access Description Indicates channel 0 conversion complete and that new data can be written to the data register. 29.5.7 DACn_IFS - Interrupt Flag Set Register Offset Bit Position 0x018 Reset Access Name Name Reset Access...
Page 724 ...the world's most energy friendly microcontrollers 29.5.9 DACn_CH0DATA - Channel 0 Data Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 DATA 0x000...
Page 725 ...the world's most energy friendly microcontrollers Name Reset Access Description 27:16 CH1DATA 0x000 Channel 1 Data Data written to this register will be written to DATA in DACn_CH1DATA. 15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 CH0DATA 0x000...
Page 726 ...the world's most energy friendly microcontrollers Name Reset Access Description Set this bit to halve the bias current. 13:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:8 OPA2BIASPROG Bias Programming Value for OPA2 These bits control the bias current level.
Page 727 ...the world's most energy friendly microcontrollers Name Reset Access Description LPF DISABLE VALUE Description PLPFDIS Disables the low pass filter between positive pad and positive input. NLPFDIS Disables the low pass filter between negative pad and negative input. 11:9 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 728 ...the world's most energy friendly microcontrollers 29.5.16 DACn_OPA0MUX - Operational Amplifier Mux Configuration Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 RESSEL OPA0 Resistor Ladder Select...
Page 729 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 RESINMUX OPA0 Resistor Ladder Input Mux These bits selects the source for the input mux to the resistor ladder Value Mode Description...
Page 730 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Resistor Value Inverting Mode Gain (-R2/R1) Non-inverting Mode Gain (1+(R2/ RES4 R2 = 3 x R1 RES5 R2 = 4 1/3 x R1 -4 1/3 5 1/3 RES6 R2 = 7 x R1 RES7 R2 = 15 x R1...
Page 731 ...the world's most energy friendly microcontrollers Name Reset Access Description POSSEL OPA1 non-inverting Input Mux These bits selects the source for the non-inverting input on OPA1 Value Mode Description DISABLE Input disabled DAC as input POSPAD POS PAD as input OPA0INP OPA0 as input OPATAP...
Page 732 ...the world's most energy friendly microcontrollers Name Reset Access Description Connects pad to the negative input mux PPEN OPA2 Positive Pad Input Enable Connects pad to the positive input mux Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 RESINMUX OPA2 Resistor Ladder Input Mux...
Page 733: Opamp - Operational Amplifier
...the world's most energy friendly microcontrollers 30 OPAMP - Operational Amplifier Quick Facts What? The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas. With flexible gain and interconnection built- in programming they can be configured to support multiple common opamp functions, with all pins available externally for filter...
Page 734: Functional Description
...the world's most energy friendly microcontrollers • Cascaded Non-inverting PGA • Two Opamp Differential Amplifier • Three Opamp Differential Amplifier • Dual Buffer ADC Driver • Programmable gain 30.3 Functional Description The three opamps can be configured to perform various opamp functions through a network of muxes. An overview of the opamps are shown in Figure 30.1 (p.
Page 735: Opamp Overview
...the world's most energy friendly microcontrollers Figure 30.2. OPAMP Overview POSSEL[2:0] POS0 PPEN POSPAD NEXTOUT0 Main output OPA0TAP OPA0 Alternative output network NEXTOUT0 NEG0 NPEN NEGPAD NEGSEL[1:0] Unity gain OPA0TAP POSSEL[2:0] POS2 PPEN POSPAD NEXTOUT1 OPA0TAP NEXTOUT0 OPA2 Main output NEG2 NPEN RESINMUX[3:0]...
Page 736 ...the world's most energy friendly microcontrollers Figure 30.3. Opamp Output Stage Overview OPA0 Main output OPA1 Main output OPA2 Main outputs ADC CH5 input m ux OPA0 OPA1 OPA2 MAIN/ ALL MAIN/ ALL MAIN OUT0 output output output OPA0 OPA1 OPA2 OUT1 OPA0 Alternative...
Page 737: Voltage Follower Unity Gain Overview
...the world's most energy friendly microcontrollers MHz when driven from a 50 ohm source. The filter adds a parasitic capacitance of approximately 1.2 pF towards local VSS when enabled. The filter is enabled out of reset and can be disabled by setting OPAxLPFDIS in DACn_OPAxCTRL.
Page 738: Inverting Input Pga Overview
...the world's most energy friendly microcontrollers 30.3.2.3 Inverting input PGA Figure 30.5 (p. 738) shows the inverting input PGA configuration. In this mode the negative input is connected to the resistor ladder by setting the OPAxNEGSEL bit-field to OPATAP in the DACn_OPAxMUX register.
Page 739: Cascaded Inverting Pga Overview
...the world's most energy friendly microcontrollers 30.3.2.5 Cascaded Inverting PGA This mode enables the opamp signals to be internally configured to cascade two or three opamps in inverting mode as shown in Figure 30.7 (p. 739) . In both cases the positive input will be configured to signal ground by setting OPAxPOSSEL bit-field to PAD in DACn_OPAx_MUX.
Page 740: Cascaded Non-Inverting Pga Overview
...the world's most energy friendly microcontrollers the last stage can be created by setting NEXTOUT in DACn_OPA1MUX and OPA2POSSEL bit-field to OPA1INP in DACn_OPA2MUX. Figure 30.8. Cascaded Non-inverting PGA Overview VOUT1= VIN(1+ R2/ R1) VOUT2= VIN(1+ R2/ R1) VOUT3= VIN(1+ R2/ R1) Table 30.6.
Page 741: Two Op-Amp Differential Amplifier Overview
...the world's most energy friendly microcontrollers Figure 30.9. Two Op-amp Differential Amplifier Overview OPA1 VDIFF= (V2- V1)R2/ R1 OPA0 OPA2 VDIFF= (V2- V1)R2/ R1 OPA1 Table 30.7. OPA0/OPA1 Differential Amplifier Configuration OPA bit-fields OPA Configuration OPA0 POSSEL POSPAD1 OPA0 NEGSEL OPA0 RESINMUX DISABLE...
Page 742: Three Op-Amp Differential Amplifier Overview
...the world's most energy friendly microcontrollers OPA2 by setting the NEXTOUT bit-field in DACn_OPA1MUX and OPA2RESINMUX to OPA1INP in DACn_OPA2MUX. In addition the OPA2POSSEL must be set to 0PATAP. The OPA2 output can be configured by configuring the OUTPEN and OUTMODE bit-field. Figure 30.10.
Page 743: Register Description
...the world's most energy friendly microcontrollers setting OPATAP in DACn_OPAxMUX. The output from the opamps can be configured to connect to the ADC by setting OUTMODE to ALT or ALL in DACn_OPAxMUX. Figure 30.11. Dual Buffer ADC Driver Overview VOUTP= VIP(1+ R2/ R1) VOUTN= VIN(1+ R2/ R1) VOUTP = VIP (Unity Gain) VOUTN = VIN (Unity Gain)
Page 744: Aes - Advanced Encryption Standard Accelerator
...the world's most energy friendly microcontrollers 31 AES - Advanced Encryption Standard Accelerator Quick Facts What? A fast and energy efficient hardware accelerator for AES-128 and AES-256 0 1 2 3 encryption and decryption. Why? Efficient encryption/decryption with little or no CPU intervention helps to meet the speed How are you? &G#% 5...
Page 745 ...the world's most energy friendly microcontrollers Figure 31.1. AES Key and Data Definitions Encryption PlainTex t CipherTex t Decryption Encryption PlainKey CipherKey Decryption 31.3.1 Encryption/Decryption The AES module can be set to encrypt or decrypt by clearing/setting the DECRYPT bit in AES_CTRL. The AES256 bit in AES_CTRL configures the size of the key used for encryption/decryption.
Page 746 ...the world's most energy friendly microcontrollers accessed through AES_KEYLn (n=A, B, C or D), while KEY7-KEY4 are accessed through KEYHn (n=A, B, C or D). Writing DATA3-DATA0 is then done through 4 consecutive writes to AES_DATA (or AES_XORDATA), starting with the word which is to be written to DATA0. For each write, the words will be word wise barrel shifted towards the least significant word.
Page 747 ...the world's most energy friendly microcontrollers • DATAWR: Cleared on a AES_DATA write or AES_CTRL write • XORDATAWR: Cleared on a AES_XORDATA write or AES_CTRL write • DATARD: Cleared on a AES_DATA read or AES_CTRL write • KEYWR: Cleared on a AES_KEYHn write or AES_CTRL write 31.3.5 Block Chaining Example Example 31.1 (p.
Page 748: Register Map
...the world's most energy friendly microcontrollers 31.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 AES_CTRL Control Register 0x004 AES_CMD Command Register 0x008 AES_STATUS Status Register 0x00C AES_IEN Interrupt Enable Register 0x010 AES_IF Interrupt Flag Register...
Page 749 ...the world's most energy friendly microcontrollers Name Reset Access Description Enable/disable key buffer in AES-128 mode. AES256 AES-256 Mode Select AES-128 or AES-256 mode. Value Description AES-128 mode AES-256 mode DECRYPT Decryption/Encryption Mode Select encryption or decryption. Value Description AES Encryption AES Decryption 31.5.2 AES_CMD - Command Register Offset...
Page 750 ...the world's most energy friendly microcontrollers 31.5.4 AES_IEN - Interrupt Enable Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DONE Encryption/Decryption Done Interrupt Enable Enable/disable interrupt on encryption/decryption done.
Page 751 ...the world's most energy friendly microcontrollers 31.5.7 AES_IFC - Interrupt Flag Clear Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DONE Encryption/Decryption Done Interrupt Flag Clear Write to 1 to clear encryption/decryption done interrupt flag...
Page 752 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 XORDATA 0x00000000 XOR Data Access Access data with XOR function through this register. 31.5.10 AES_KEYLA - KEY Low Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:0 KEYLA...
Page 753 ...the world's most energy friendly microcontrollers 31.5.12 AES_KEYLC - KEY Low Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:0 KEYLC 0x00000000 Key Low Access C Access the low key words through this register. 31.5.13 AES_KEYLD - KEY Low Register Offset Bit Position 0x03C...
Page 754 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 KEYHA 0x00000000 Key High Access A Access the high key words through this register. 31.5.15 AES_KEYHB - KEY High Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:0...
Page 755 ...the world's most energy friendly microcontrollers 31.5.17 AES_KEYHD - KEY High Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:0 KEYHD 0x00000000 Key High Access D Access the high key words through this register. www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 756: Gpio - General Purpose Input/Output
...the world's most energy friendly microcontrollers 32 GPIO - General Purpose Input/Output Quick Facts What? The GPIO (General Purpose Input/Output) is used for pin configuration and direct pin manipulation and sensing as well as routing 0 1 2 3 for peripheral pin connections. Why? Easy to use and highly configurable input/ output pins are important to fit many...
Page 757: Functional Description
...the world's most energy friendly microcontrollers • EM4 IO pin retention. This includes • Output enable • Output value • Pull enable • Pull direction • EM4 wake-up on selected GPIO pins • Glitch suppression input filter. • Analog connection to e.g. ADC. •...
Page 758: Pin Configuration
...the world's most energy friendly microcontrollers Figure 32.1. Pin Configuration Alternate function override Alternate function output enable Alternate function data out Port Control Output enable Output enable Data out Output value DOUT protection Pull- up enable Pull- down enable MODEn[3:0] Input enable protection Filter enable...
Page 759: Open-Drain
...the world's most energy friendly microcontrollers MODEn Input Output DOUT Pull- Pull- Alt. Input Description down strength Filter 0b0011 Input enabled with pull-down and filter Input enabled with pull-up and filter 0b0100 Push-pull Push-pull 0b0101 Push-pull with alt. drive strength 0b0110 Open Open-source...
Page 760 ...the world's most energy friendly microcontrollers Figure 32.3. Push-Pull Configuration Output Enable DOUT Input Enable When MODEn is 0110 or 0111, the pin operates in open-source mode, the latter with a pull-down resistor. When driving a high value in open-source mode, the pull-down is disconnected to save power. For the remaining MODEn values, i.e.
Page 761 ...the world's most energy friendly microcontrollers Figure 32.5. EM4 Wake-up Logic GPIO_EM4WUCAUSE GPIO_CMD GPIO_EM4WUEN GPIO_EM4WUPOL Wake- up Logic Wake- up request The pins used for EM4 wake-up must be configured as inputs using the GPIO_Px_MODEL/ GPIO_Px_MODEH register. Before going down to EM4, it is important to clear the wake-up logic by setting the EM4WUCLR bitfield in the GPIO_CMD register, which clears the complete wake-up logic, including the GPIO_EM4WUCAUSE register.
Page 762 ...the world's most energy friendly microcontrollers It is possible, but not recommended to select two or more peripherals as output on the same pin. These signals will then be OR'ed together. However, TIMER CCx and CDTIx outputs, which are routed as alternate functions, have priority, and will never be OR'ed with other alternate functions.
Page 763 ...the world's most energy friendly microcontrollers All pins with the same pin number (n) are grouped together to trigger one interrupt flag (EXT[n] in GPIO_IF). The EXTIPSELn[2:0] bits in GPIO_EXTIPSELL or GPIO_EXTIPSELH select which port will trigger the interrupt flag. The GPIO_EXTIRISE[n] and GPIO_EXTIFALL[n] registers enables sensing of rising and falling edges.
Page 764: Register Map
...the world's most energy friendly microcontrollers 32.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 GPIO_PA_CTRL Port Control Register 0x004 GPIO_PA_MODEL Port Pin Mode Low Register 0x008 GPIO_PA_MODEH Port Pin Mode High Register 0x00C GPIO_PA_DOUT Port Data Out Register...
Page 765: Register Description
...the world's most energy friendly microcontrollers Offset Name Type Description 0x0A0 GPIO_PE_DOUTSET Port Data Out Set Register 0x0A4 GPIO_PE_DOUTCLR Port Data Out Clear Register 0x0A8 GPIO_PE_DOUTTGL Port Data Out Toggle Register 0x0AC GPIO_PE_DIN Port Data In Register 0x0B0 GPIO_PE_PINLOCKN Port Unlocked Pins Register 0x0B4 GPIO_PF_CTRL Port Control Register...
Page 766 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DRIVEMODE Drive Mode Select Select drive mode for all pins on port configured with alternate drive strength. Value Mode Description...
Page 767 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description WIREDANDDRIVEFILTER Open-drain output with filter and drive-strength set by DRIVEMODE WIREDANDDRIVEPULLUP Open-drain output with pullup and drive-strength set by DRIVEMODE WIREDANDDRIVEPULLUPFILTER Open-drain output with filter, pullup and drive-strength set by DRIVEMODE 32.5.3 GPIO_Px_MODEH - Port Pin Mode High Register Offset Bit Position...
Page 768 ...the world's most energy friendly microcontrollers 32.5.4 GPIO_Px_DOUT - Port Data Out Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DOUT 0x0000...
Page 769 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DOUTCLR 0x0000 Data Out Clear Write bits to 1 to clear corresponding bits in GPIO_Px_DOUT. Bits written to 0 will have no effect. 32.5.7 GPIO_Px_DOUTTGL - Port Data Out Toggle Register Offset Bit Position...
Page 770 ...the world's most energy friendly microcontrollers 32.5.9 GPIO_Px_PINLOCKN - Port Unlocked Pins Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 PINLOCKN 0xFFFF...
Page 771 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 22:20 EXTIPSEL5 External Interrupt 5 Port Select Select input port for external interrupt 5. Value Mode Description...
Page 772 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PORTF Port F pin 1 selected for external interrupt 1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) EXTIPSEL0 External Interrupt 0 Port Select Select input port for external interrupt 0.
Page 773 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PORTA Port A pin 13 selected for external interrupt 13 PORTB Port B pin 13 selected for external interrupt 13 PORTC Port C pin 13 selected for external interrupt 13 PORTD Port D pin 13 selected for external interrupt 13 PORTE...
Page 774 ...the world's most energy friendly microcontrollers Name Reset Access Description Select input port for external interrupt 8. Value Mode Description PORTA Port A pin 8 selected for external interrupt 8 PORTB Port B pin 8 selected for external interrupt 8 PORTC Port C pin 8 selected for external interrupt 8 PORTD...
Page 775 ...the world's most energy friendly microcontrollers Name Reset Access Description Set bit n to enable triggering of external interrupt n on falling edge. Value Description EXTIFALL[n] = 0 Falling edge trigger disabled EXTIFALL[n] = 1 Falling edge trigger enabled 32.5.14 GPIO_IEN - Interrupt Enable Register Offset Bit Position 0x110...
Page 776 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description EXT[n] = 1 Pin n external interrupt flag set 32.5.16 GPIO_IFS - Interrupt Flag Set Register Offset Bit Position 0x118 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 777 ...the world's most energy friendly microcontrollers 32.5.18 GPIO_ROUTE - I/O Routing Register Offset Bit Position 0x120 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 25:24 ETMLOCATION I/O Location...
Page 778 ...the world's most energy friendly microcontrollers Name Reset Access Description Enable Serial Wire Clock connection to pin. WARNING: When this pin is disabled, the device can no longer be accessed by a debugger. A reset will set the pin back to a default state as enabled. If you disable this pin, make sure you have at least a 3 second timeout at the start of you program code before you disable the pin.
Page 779 ...the world's most energy friendly microcontrollers 32.5.21 GPIO_CTRL - GPIO Control Register Offset Bit Position 0x12C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) EM4RET Enable EM4 retention Set to enable EM4 retention of output enable, output value and pull enable.
Page 780 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 0x01 Enable em4 wakeup on pin A0 0x02 Enable em4 wakeup on pin A6 0x04 Enable em4 wakeup on pin C9 0x08 Enable em4 wakeup on pin F1 0x10 Enable em4 wakeup on pin F2 0x20...
Page 781 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 0x01 This bit indicates an em4 wake-up request occurred on pin A0 0x02 This bit indicates an em4 wake-up request occurred on pin A6 0x04 This bit indicates an em4 wake-up request occurred on pin C9 0x08 This bit indicates an em4 wake-up request occurred on pin F1 0x10...
Page 782: Lcd - Liquid Crystal Display Driver
...the world's most energy friendly microcontrollers 33 LCD - Liquid Crystal Display Driver Quick Facts What? The LCD driver can drive up to 8x36 segmented LCD directly. The LCD driver consumes less than 900 nA in EM2. The animation feature makes it possible to have active animations without CPU intervention.
Page 783: Functional Description
...the world's most energy friendly microcontrollers • Frame Counter • LCD frame interrupt • Direct segment control 33.3 Functional Description An overview of the LCD module is shown in Figure 33.1 (p. 783) . In its simplest form, an LCD driver would apply a voltage above a certain threshold voltage in order to darken a segment and a voltage below threshold to make a segment clear.
Page 784 ...the world's most energy friendly microcontrollers Each LCD segment pin can also be individually disabled by setting the pin to any other state than DISABLED in the GPIO pin configuration. 33.3.2 Multiplexing, Bias, and Wave Settings The LCD driver supports different multiplexing and bias settings, and these can be set individually in the MUX and BIAS bits in LCD_DISPCTRL respectively, see Table 33.1 (p.
Page 785 ...the world's most energy friendly microcontrollers Table 33.3. LCD Wave Settings WAVE Mode Wave mode LowPower Low power optimized waveform output Normal Regular waveform output Figure 33.2. LCD Low-power Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias (2/ 3V (1/ 3V Fram e Start Fram e End...
Page 786: Lcd 1/2 Bias And Duplex Multiplexing - Lcd_Seg0
...the world's most energy friendly microcontrollers 33.3.3.2 Waveforms with 1/2 Bias and Duplex Multiplexing In this mode, each frame is divided into 4 periods. LCD_COM[1:0] lines can be multiplexed with all segment lines. Figures show 1/2 bias and duplex multiplexing (waveforms show two frames) Figure 33.5.
Page 787 ...the world's most energy friendly microcontrollers 1/2 bias and duplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) • V = 0.79 × V LCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform. Figure 33.9.
Page 788: Lcd 1/3 Bias And Duplex Multiplexing - Lcd_Seg0
...the world's most energy friendly microcontrollers Figure 33.12. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM1 (2/ 3V (1/ 3V Fram e Start Fram e End 1/3 bias and duplex multiplexing - LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels.
Page 789 ...the world's most energy friendly microcontrollers Figure 33.15. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 (2/ 3V (1/ 3V (1/ 3V (2/ 3V Fram e Start Fram e End 1/3 bias and duplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) •...
Page 790: Lcd 1/2 Bias And Triplex Multiplexing - Lcd_Seg0
...the world's most energy friendly microcontrollers Figure 33.19. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM2 (1/ 2V Fram e Start Fram e End 1/2 bias and triplex multiplexing - LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels.
Page 791 ...the world's most energy friendly microcontrollers 1/2 bias and triplex multiplexing - LCD_SEG0-LCD_COM1 • DC voltage = 0 (over one frame) • V = 0.7 V LCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be ON with this waveform Figure 33.23.
Page 792: Lcd 1/3 Bias And Triplex Multiplexing - Lcd_Seg0
...the world's most energy friendly microcontrollers Figure 33.26. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM1 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 33.27. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM2 (2/ 3V (1/ 3V Fram e Start Fram e End 1/3 bias and triplex multiplexing - LCD_SEG0...
Page 793 ...the world's most energy friendly microcontrollers Figure 33.30. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0 (2/ 3V (1/ 3V (1/ 3V (2/ 3V Fram e Start Fram e End 1/3 bias and triplex multiplexing - LCD_SEG0-LCD_COM1 • DC voltage = 0 (over one frame) •...
Page 794 ...the world's most energy friendly microcontrollers Figure 33.33. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM0 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 33.34. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM1 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 33.35.
Page 795: Lcd 1/3 Bias And Quadruplex Multiplexing - Lcd_Seg0
...the world's most energy friendly microcontrollers Figure 33.37. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 33.38. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 Connection com 0 com 1 com 2 com 3 1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM0...
Page 796: Lcd Contrast
...the world's most energy friendly microcontrollers Figure 33.40. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM1 (2/ 3V (1/ 3V (1/ 3V (2/ 3V Fram e Start Fram e End 1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM2 • DC voltage = 0 (over one frame) •...
Page 797 ...the world's most energy friendly microcontrollers adjusts the V . The contrast is set by CONLEV in LCD_DISPCTRL, and can be adjusted relative LCD_OUT to either V ) or Ground using CONCONF in LCD_DISPCTRL. See Table 33.4 (p. 797) and Table 33.5 (p.
Page 798 ...the world's most energy friendly microcontrollers Table 33.6. LCD Principle of Contrast Adjustment for Different Bias Settings. Contrast adjustment Contrast adjustment No contrast adjustment relative to V relative to GND (CONLEV = 11111) (CONCONF = 0) (CONCONF = 1) 1/4 bias LCD_OUT LCD_OUT LCD_OUT...
Page 799 ...the world's most energy friendly microcontrollers 33.3.5 V Selection By default, the LCD driver runs on main external power (V ), see Table 33.7 (p. 799) . An internal boost circuit can be enabled by setting VBOOSTEN in CMU_LCDCTRL and selecting the boosted voltage by setting VLCDSEL in LCD_DISPCTRL.
Page 800: Lcd Frame Rate Calculation
...the world's most energy friendly microcontrollers • LFCLK16: LFACLK = LFACLK/16 LCDpre • LFCLK32: LFACLK = LFACLK/32 LCDpre • LFCLK64: LFACLK = LFACLK/64 LCDpre • LFCLK128: LFACLK = LFACLK/128 LCDpre In addition to selecting the correct prescaling, the clock source can be selected in the CMU. To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.
Page 801 ...the world's most energy friendly microcontrollers Table 33.10. LCD Update Data Control (UDCTRL) Bits UDCTRL Mode Description REGULAR The data transfer is controlled by SW and data synchronization is initiated by writing data to the buffers. Data is transferred as soon as possible, possibly creating a frame with a DC component on the LCD.
Page 802: Lcd Event Frequency Equation
...the world's most energy friendly microcontrollers Table 33.12. FCPRESC FCPRESC Mode Description General equation Div1 FRAME Div2 FRAME FCPRESC = CLK FRAME Div4 FRAME Div8 FRAME The top value for the Frame Counter is set by FCTOP in LCD_BACTRL. Every time the frame counter reaches zero, it is reloaded with the top value, and at the same time an event, which can cause an interrupt, data update, blink, or an animation state transition is triggered.
Page 803 ...the world's most energy friendly microcontrollers 33.3.12 Blink, Blank, and Animation Features 33.3.12.1 Blink The LCD driver can be configured to blink, alternating all enabled segments between on and off. The blink frequency is given by the CLK frequency, see Section 33.3.10 (p. 801) . See Section 33.3.8 (p. EVENT 800) for details regarding synchronization of the blink feature.
Page 804 ...the world's most energy friendly microcontrollers cleared when LCD_AREGA or LCD_AREGB are updated with new values. See Table 33.15 (p. 804) for an example. Table 33.15. LCD Animation Example ASTATE LCD_AREGA LCD_AREGB Resulting Data 11000000 11000000 11000000 01100000 11000000 11100000 01100000 01100000 01100000...
Page 805 ...the world's most energy friendly microcontrollers Example 33.2. LCD Animation Enable Example • Write data into the animation registers LCD_AREGA, LCD_AREGB • Enable the correct shift direction (if any) • Decide which logical function to perform on the registers • ALOGSEL = 0: Data_out = LCD_AREGA & LCD_AREGB •...
Page 806: Register Map
...the world's most energy friendly microcontrollers 33.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LCD_CTRL Control Register 0x004 LCD_DISPCTRL Display Control Register 0x008 LCD_SEGEN Segment Enable Register 0x00C LCD_BACTRL Blink and Animation Control Register 0x010 LCD_STATUS...
Page 807 ...the world's most energy friendly microcontrollers Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Direct Segment Control This bit enables direct control over bias levels for each SEG/COM line.
Page 808 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description LEVEL0 Minimum boost level LEVEL1 LEVEL2 LEVEL3 LEVEL4 LEVEL5 LEVEL6 LEVEL7 Maximum boost level Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) VLCDSEL Selection This bit controls which Voltage source that is connected to V...
Page 809 ...the world's most energy friendly microcontrollers Name Reset Access Description MUXE Mode Description SEXTAPLEX Sextaplex. Uses com lines LCD_COM0- LCD_COM5. OCTAPLEX Octaplex. Uses com lines LCD_COM0- LCD_COM7. 33.5.3 LCD_SEGEN - Segment Enable Register Offset Bit Position 0x008 Reset Access Name Name Reset Access...
Page 810 ...the world's most energy friendly microcontrollers Name Reset Access Description 17:16 FCPRESC Frame Counter Prescaler These bits controls the prescaling value for the Frame Counter input clock. Value Mode Description DIV1 = CLK FRAME DIV2 = CLK FRAME DIV4 = CLK FRAME DIV8 = CLK...
Page 811 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) BLINK Blink State This bits indicates the blink status. If this bit is 1, all segments are off. If this bit is 0, the segments(LCD_SEGDxn) which are set to 1 are on.
Page 812 ...the world's most energy friendly microcontrollers 33.5.8 LCD_IF - Interrupt Flag Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Frame Counter Interrupt Flag Set when Frame Counter is zero.
Page 813 ...the world's most energy friendly microcontrollers 33.5.11 LCD_IEN - Interrupt Enable Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Frame Counter Interrupt Enable Set to enable interrupt on frame counter interrupt flag.
Page 814 ...the world's most energy friendly microcontrollers Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:0 SEGD1L 0x00000000 COM1 Segment Data Low This register contains segment data for segment lines 0-31 for COM1. 33.5.14 LCD_SEGD2L - Segment Data Low Register 2 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 815 ...the world's most energy friendly microcontrollers Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:0 SEGD3L 0x00000000 COM3 Segment Data Low This register contains segment data for segment lines 0-31 for COM3. 33.5.16 LCD_SEGD0H - Segment Data High Register 0 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 816 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SEGD1H 0x00 COM1 Segment Data High This register contains segment data for segment lines 32-39 for COM1. 33.5.18 LCD_SEGD2H - Segment Data High Register 2 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 817 ...the world's most energy friendly microcontrollers 33.5.20 LCD_FREEZE - Freeze Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) REGFREEZE Register Update Freeze When set, the update of the LCD is postponed until this bit is cleared.
Page 818 ...the world's most energy friendly microcontrollers Name Reset Access Description SEGD3H SEGD3H Register Busy Set when the value written to SEGD3H is being synchronized. SEGD2H SEGD2H Register Busy Set when the value written to SEGD2H is being synchronized. SEGD1H SEGD1H Register Busy Set when the value written to SEGD1H is being synchronized.
Page 819 ...the world's most energy friendly microcontrollers Offset Bit Position 0x0B8 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SEGD5H 0x00 COM1 Segment Data High This register contains segment data for segment lines 32-39 for COM1.
Page 820 ...the world's most energy friendly microcontrollers Name Reset Access Description SEGD7H 0x00 COM3 Segment Data High This register contains segment data for segment lines 32-39 for COM3. 33.5.26 LCD_SEGD4L - Segment Data Low Register 4 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x0CC...
Page 821 ...the world's most energy friendly microcontrollers Offset Bit Position 0x0D4 Reset Access Name Name Reset Access Description 31:0 SEGD6L 0x00000000 COM6 Segment Data This register contains segment data for segment lines 0-23 for COM6. 33.5.29 LCD_SEGD7L - Segment Data Low Register 7 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 822: Revision History
...the world's most energy friendly microcontrollers 34 Revision History 34.1 Revision 1.20 April 28th, 2016 Updated memory system map Added revision E Replaced static bit write instruction with reference to the Cortex-M3 manual Updated GPIO pin configuration schematic Corrected UD, LB and DI flash addresses in the MSC section. Added full wafer as package option.
Page 823: Revision 1.00
...the world's most energy friendly microcontrollers 34.3 Revision 1.00 August 28th, 2013 Updated 1 MHz band bitfield description in CMU_HFRCOBAND and CMU_AUXBAND register. Updated 7 MHz band bitfield description in CMU_HFRCOBAND and CMU_AUXBAND register. Updated 1 MHz HFRCOBAND and AUXHFRCOBAND to 1.2 MHz in the DI table. Updated 7 MHz HFRCOBAND and AUXHFRCOBAND to 6.6 MHz in the DI table.
Page 824: Revision 0.95
...the world's most energy friendly microcontrollers Changed default value for LFXOBOOST in CMU_CTRL. Updated register description for the DMA controller. 34.5 Revision 0.95 January 24th, 2012 Updated EMU Energy Mode Overview table. Updated EMU Wakeup Triggers from Low Energy Modes table. Corrected UART data frame rate.
Page 825 ...the world's most energy friendly microcontrollers Initial preliminary revision. www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 826: Abbreviations
...the world's most energy friendly microcontrollers A Abbreviations A.1 Abbreviations This section lists abbreviations used in this document. Table A.1. Abbreviations Abbreviation Description ACMP Analog Comparator Analog to Digital Converter AMBA Advanced High-performance Bus. AMBA is short for "Advanced Microcontroller Bus Architecture".
Page 827 ...the world's most energy friendly microcontrollers Abbreviation Description LETIMER Low Energy Timer LEUART Low Energy Universal Asynchronous Receiver Transmitter LFRCO Low Frequency RC Oscillator LFXO Low Frequency Crystal Oscillator Low-speed Media Access Controller NVIC Nested Vector Interrupt Controller OPA/OPAMP Operational Amplifier Oversampling Ratio On-the-go PCNT...
Page 828: Disclaimer And Trademarks
A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Page 829: Contact Information
...the world's most energy friendly microcontrollers C Contact Information Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Please visit the Silicon Labs Technical Support web page: http://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 830: Table Of Contents
...the world's most energy friendly microcontrollers Table of Contents 1. Energy Friendly Microcontrollers ........................2 1.1. Typical Applications ......................... 2 1.2. EFM32GG Development ........................2 2. About This Document ..........................3 2.1. Conventions ........................... 3 2.2. Related Documentation ........................4 3.
Page 831 ...the world's most energy friendly microcontrollers 13.2. Features ..........................164 13.3. Functional Description ........................ 164 13.4. Register Map ..........................169 13.5. Register Description ........................169 14. EBI - External Bus Interface ........................175 14.1. Introduction ..........................175 14.2. Features ..........................175 14.3.
Page 832 ...the world's most energy friendly microcontrollers 25.3. Functional description ......................... 624 25.4. Register Map ..........................639 25.5. Register Description ........................640 26. ACMP - Analog Comparator ........................669 26.1. Introduction ..........................669 26.2. Features ..........................669 26.3. Functional Description ........................ 670 26.4.
Page 833 ...the world's most energy friendly microcontrollers List of Figures 3.1. Block Diagram of EFM32GG ........................5 3.2. Energy Mode Indicator ..........................5 3.3. Revision Number Extraction ........................10 4.1. Interrupt Operation ..........................13 5.1. EFM32GG Bus System .......................... 16 5.2. System Address Space .......................... 17 5.3.
Page 834 ...the world's most energy friendly microcontrollers 14.33. EBI TFT Size ..........................201 14.34. EBI TFT Direct Drive from Internal Memory ................... 202 14.35. EBI TFT Direct Drive from External Memory (non-multiplexed address/data) ..........203 14.36. EBI TFT Direct Drive from External Memory (multiplexed address/data) ............203 14.37.
Page 835 ...the world's most energy friendly microcontrollers 17.14. USART SmartCard Stop Bit Sampling ....................465 17.15. USART SPI Timing .......................... 467 17.16. USART Standard I2S waveform ......................469 17.17. USART Standard I2S waveform (reduced accuracy) ................470 17.18. USART Left-justified I2S waveform ...................... 470 17.19.
Page 836 ...the world's most energy friendly microcontrollers 27.1. VCMP Overview ..........................681 27.2. VCMP 20 mV Hysteresis Enabled ......................682 28.1. ADC Overview ..........................690 28.2. ADC Conversion Timing ........................691 28.3. ADC Analog Power Consumption With Different WARMUPMODE Settings ............ 692 28.4.
Page 837 ...the world's most energy friendly microcontrollers 33.44. LCD Block Diagram of the Animation Circuit ..................804 www.silabs.com 2016-04-28 - Giant Gecko Family - d0053_Rev1.20...
Page 838 ...the world's most energy friendly microcontrollers List of Tables 2.1. Register Access Types ..........................3 3.1. Energy Mode Description ......................... 8 3.2. EFM32GG Microcontroller Series ....................... 8 3.3. Minor Revision Number Interpretation ....................... 11 4.1. Interrupt Request Lines (IRQ) ........................13 5.1.
Page 839 ...the world's most energy friendly microcontrollers 20.3. TIMER Events ........................... 541 21.1. RTC Resolution Vs Overflow ....................... 563 22.1. Resolution and overflow ........................572 23.1. LETIMER Repeat Modes ........................587 23.2. LETIMER Underflow Output Actions ...................... 592 24.1. PCNT QUAD Mode Counter Control Function ..................611 25.1.
Page 840 ...the world's most energy friendly microcontrollers List of Examples 8.1. DMA Transfer ............................70 17.1. USART Multi-processor Mode Example ....................463 20.1. TIMER DTI Example 1 ........................539 20.2. TIMER DTI Example 2 ........................539 23.1. LETIMER Triggered Output Generation ....................595 23.2.
Page 841 ...the world's most energy friendly microcontrollers List of Equations 5.1. Memory SRAM Area Set/Clear Bit ......................17 5.2. Memory Peripheral Area Bit Modification ....................18 5.3. Memory Wait Cycles with Clock Equal or Faster than HFCORECLK ............... 20 5.4. Memory Wait Cycles with Clock Slower than CPU ..................20 12.1.
Page 843 X-ON Electronics Largest Supplier of Electrical and Electronic Components Click to view similar products for category: Daughter Cards & OEM Boards Click to view products by manufacturer: Silicon Labs Other Similar products are found below : ADZS-21262-1-EZEXT 27911 MPC5777C-416DS KITMPC5744DBEVM SPC56ELADPT144S TMDXRM46CNCD DM160216 MPC5777M-416DS EV-ADUCM350GPIOTHZ EV-ADUCM350-BIO3Z ATSTK521 1130 MA160015 MA180033 MA240013 MA240026 MA320014 MA330014 MA330017 TLK10034SMAEVM TMDSCNCD28054MISO MIKROE-2152 MIKROE-2154 MIKROE-2381 TSSOP20EV DEV-11723 MIKROE-1108 MIKROE-1516 SPS-READER-GEVK AC244049 AC244050 AC320004-3 2077...

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