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User Guide
SETTING UP THE EVAL-ADAU1861EBZ EVALUATION BOARD
INSTALLING THE LARK STUDIO SOFTWARE
Take the following steps to download and install the latest version of
the Lark Studio GUI tool:
1. Go to the
ADAU1861
web page and download the latest ver-
sion of the Lark Studio GUI tool found within the Software &
Systems Requirements section.
2. Download the latest version of the Lark Studio zip file and run
the lark_studio executable file within. Follow the prompts, in-
cluding accepting the license agreement, to install the software.
Table 1. Default Switch and Jumper Settings
Jumper and Switch Connections
Pin 2 to Pin 3 of JP5
Pin 1 to Pin 2 of JP6
Pin 1 to Pin 2 of JP7
Pin 1 to Pin 2 of JP8
Pin 1 to Pin 2 of JP9 and Pin 1 to Pin 2 of JP11
Pin 1 to Pin 2 of JP22
Pin 1 to Pin 2 of JP24
Pin 1 to Pin 2 of JP25
Pin 1 to Pin 2 of JP38 and Pin 2 to Pin 3 of JP39
Pin 2 to Pin 3 of JP40
Pin 2 to Pin 3 of JP41
JP42 connected
Pin 1 to Pin 2 of JP1, Pin 1 to Pin 2 of JP26, Pin 1 to Pin 2 of JP27, Pin 1 to Pin 2 of JP28
S1 Up (SPI)
Pin 1 of S4 to GND and Pin 2 of S4 to GND
Pin 1 of S5 to GND and Pin 2 of S5 to GND, Pin 3 of S5 to GND and Pin 4 of S5 to GND
Pin 1 of S6 to GND and Pin 2 of S6 to GND, Pin 3 of S6 to GND and Pin 4 of S6 to GND
Pin 1 of S7 to GND and Pin 2 of S7 to GND, Pin 3 of S7 to GND and Pin 4 of S7 to GND
Pin 1 of S8 to GND and Pin 2 of S8 to GND, Pin 3 of S8 to GND and Pin 4 of S8 to GND
analog.com
EVAL-ADAU1861
INSTALLING THE USB DRIVERS
If the USB interface is not recognized by the Lark Studio GUI
tool software and the PC, go to the Future Technology Devices
International (FTDI) Limited chip official web page and download
the relevant drivers.
DEFAULT SWITCH AND JUMPER SETTINGS
Table 1
shows the default switch and jumper settings.
Option Selected
The P4 interface works in mono mode with ADC0
ADC2 differential mode
ADC1 differential mode
ADC0 differential mode
Use JP9 and JP11 as the main clock (24.576 MHz oscillator) source paths
REG_EN disabled and DVDD supplied with on-board LDO
SELFBOOT disabled
ROM_BOOT_MODE disabled
AVDD and IOVDD supplied by the 1.8 V on-board low-dropout (LDO)
regulator (JP38 and JP39）
DVDD supplied by the 0.9 V on-board LDO regulator
HPVDDL supplied by the 1.3 V on-board LDO regulator
IOVDD_1861 supplied with an IOVDD on-board LDO regulator
2
I
C and SPI communication
SPI communication
2
Set I
C address
I2S0 port, 1.8 V to 3.3 V
I2S1 port, 1.8 V to 3.3 V
DMIC port, 1.8 V to 3.3 V
PDM port, 1.8 V to 3.3 V
Rev. 0 | 4 of 24
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