Alinx UltraScale+ AXU4EV-P User Manual page 43

Configuration Pin
PHYAD[2:0]
CLK125_EN
LED_MODE
MODE0~MODE3
When the network is connected to Gigabit Ethernet, the data transmission
of ZYNQ and PHY chip KSZ9031RNX is communicated through the RGMII bus,
the transmission clock is 125Mhz, and the data is sampled on the rising edge
and falling samples of the clock.
When the network is connected to 100M Ethernet, the data transmission of
ZYNQ and PHY chip KSZ9031RNX is communicated through RMII bus, and
the transmission clock is 25Mhz. Data is sampled on the rising edge and falling
samples of the clock.
U1
ZYNQ
Ultra
Scale+
Figure 3-5-1: ZYNQ PS system and GPHY connection diagram
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ZYNQ Ultrascale + FPGA Board AXU4EV-P User Manual
Instructions
MDIO/MDC Mode PHY Address
Enable 125Mhz clock output selection
LED light mode configuration
Link adaptation and full duplex
configuration
Table 3-5-1: PHY chip default configuration value
RGMII TX
BANK
502
RGMII RX
RGMII TX
BANK
66
RGMII RX
Configuration value
PHY Address 011
Enable
Single LED light mode
10/100/1000 adaptive, compatible
with full-duplex, half-duplex
U4
GPHY
(KSZ9031RNX)
U22
GPHY
(KSZ9031RNX)
J6
J11
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