Quectel BG772A-GL Hardware Design page 43

MAIN_RI* 76
NOTE
AT+IPR command can be used to set the baud rate of the main UART interface, and AT+IFC command
can be used to set the hardware flow control (the function is disabled by default). See document [4] for
more details about these AT commands.
Table 14: Pin Definition of Debug UART Interface
Pin Name Pin No.
DBG_TXD 60
DBG_RXD 61
DBG_CTS 51
DBG_RTS 92
Table 15: Pin Definition of
Pin Name Pin No.
AUX_TXD 93
AUX_RXD 82
AUX_CTS 70
AUX_RTS 59
The module provides 1.8 V UART interfaces. A voltage-level translator should be used if customers'
application is equipped with a 3.3 V UART interface. The following figure shows a reference design of the
main UART interface:
BG772A-GL_Hardware_Design
DO/PU Main UART ring indication
I/O Description
DO/PU Debug UART transmit
DI/PU Debug UART receive
DO/PU Debug UART clear to send
DI/PD Debug UART request to send
Auxiliary
UART Interface
I/O Description
DO/PU Auxiliary UART transmit
DI/PU Auxiliary UART receive
DO/PU Auxiliary UART clear to send
DI/PU Auxiliary UART request to send
LPWA Module Series
BG772A-GL Hardware Design
Comment
1.8 V power domain
Comment
1.8 V power domain
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