Pon_Trig - Quectel BG772A-GL Hardware Design

Figure 11: Reference Circuit of RESET_N by Using Button
NOTE
Ensure that there is no large capacitance on RESET_N pin.

3.8. PON_TRIG*

BG772A-GL provides one PON_TRIG pin which is used to wake up the module from PSM. When the pin
detects high level for minimum assertion time 100 μs, the module will wake up from PSM.
Table 10: Pin Definition of PON_TRIG
Pin Name Pin No.
PON_TRIG 72
BG772A-GL_Hardware_Design
I/O Description
Wake up the module from
DI/NP
PSM
LPWA Module Series
BG772A-GL Hardware Design
Comment
1.8 V power domain.
Wakeup active high for minimum
assertion time 100 μs .
No pulled by default.
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