Keep Last Status (Jp1); Port Direction Settings (Jp2~Jp25) - Advantech PCIE-1753 User Manual

3.2.1

Keep Last Status (JP1)

Jumper JP1 gives the PCIE-1753 a new and valuable function. With JP1 enabled,
PCIE-1753 "memorizes" all I/O port settings and output values, and, in the event of a
"hot" reset, the settings and output values present at the port just prior to reset are
restored to each port following the reset. This feature applies to both ports set by soft-
ware, and to ports configured as output ports via jumper. Depending on the applica-
tion, this function may allow a card to be reset without requiring a complete shutdown
of processes controlled by the card (since port values are left unchanged and are
interrupted only momentarily). Complete loss of power to the card clears chip mem-
ory. Thus, even if JP1 is enabled, the card's power-on state will return to the default
state or the state of an output port with voltage low output (for jumper-set ports).
When jumper JP1 is disabled, power-off or reset results in ports returning to their
default state (for software-set ports) or returning to the state of the output port with
low voltage output (for jumper-set ports).
Table 3.1: Power-On Configuration (JP1)
Jumper Setting
*Default setting.
3.2.2

Port Direction Settings (JP2~JP25)

Table 3.2: DI/O Channel Direction Configuration (JP2 ~ JP25)
Jumpers
JP2, JP3
JP4, JP5
JP6, JP7
JP8, JP9
JP10, JP11
JP12, JP13
JP14, JP15
JP16, JP17
JP18, JP19
JP20, JP21
JP22, JP23
JP24, JP25
Description
Keep the last status after a hot reset.
Reset to default status after a hot reset.*
Controlled DI/O channels
Port 0 DI/O 0 ~ DI/O 7
Port 1 DI/O 0 ~ DI/O 7
Port 2 DI/O 0 ~ DI/O 7
Port 3 DI/O 0 ~ DI/O 7
Port 4 DI/O 0 ~ DI/O 7
Port 5 DI/O 0 ~ DI/O 7
Port 6 DI/O 0 ~ DI/O 7
Port 7 DI/O 0 ~ DI/O 7
Port 8 DI/O 0 ~ DI/O 7
Port 9 DI/O 0 ~ DI/O 7
Port 10 DI/O 0 ~ DI/O 7
Port 11 DI/O 0 ~ DI/O 7
13 PCIE-1753 User Manual