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Device Configuration
4 Device Configuration
The DAC device is programmable through the serial programming interface (SPI) bus accessible through the
FTDI USB-to-SPI converter located on the FTDI dongle. A GUI is provided to write instructions on the bus and
program the registers of the DAC device.
For more information about the registers in the ADC device, see the
4.1 Supported JESD204C Device Features
The DAC device supports some configuration of the JESD204C interface. Due to limitations in the
TSW14J59EVM firmware, all JESD204C link features of the DAC device are not supported.
the supported and non-supported features.
Table 4-1. Supported and Non-Supported Features of the JESD204C Device
JESD204C Feature
Number of lanes per link (L)
Scrambling
Test patterns
Speed
(1)
Dependent on bypass or decimation mode and output rate selection. Always disable the JESD204 block before changing any of the
JESD204C settings. Once the settings are changed, re-enable the JESD204 block.
4.2 Tab Organization
Control of the DAC device features are available in the JMode, NCO and RX tabs.
4.3 Register Map and Console Control
The Register Map tab, illustrated in
time, the controls in
Table 4-2
The Console tab logs all the SPI reads and writes which are performed when various devices are programmed
on the DAC EVM . The config files can saved and loaded from the console tab.
Control
Register map summary
Write register button
Write all button
Read register button
Read-all button
Load Configuration button
Save Configuration button
Register Data cluster
Individual register cluster with
read or write register buttons
16
DAC39RF10EVM Evaluation Module
Supported by DAC Device
L = 1, 2, 3, 4, 6, 8,12,16
Supported
PRBS7, PRBS9, PRBS15, PRBS31
Lane rates from 0.75 to 12.8 Gbps
Figure
4-1, allows configuration of the devices at the bit-field level. At any
can be used to configure or read from the device.
Table 4-2. Register Map and Console Controls
Description
Displays the devices on the EVM, registers for those devices, and the states of the registers
•
Clicking on a register field allows individual bit manipulation in the register data cluster
•
The value column shows the value of the register at the time the GUI was last updated
•
The LR column shows the value of the register at the time the register was last read
Write to the register highlighted in the register map summary with the value in the Write Data field
Update all registers shown in the register map summary with the values shown in the Register Map
summary
Read from the register highlighted in the Register Map summary and display the results in the Read Data
field
Can be used to re-synchronize the GUI with the state of the hardware
Read from all registers in the Register Map summary and display the current state of the hardware
Load a configuration file from disk and register address/data values in the file
Save a configuration file to disk that contains the current state of the configuration registers
Manipulate individual accessible bits of the register highlighted in the register map summary
Perform a generic read or write command to the device shown in the Block drop-down box using the
address and write data information
Copyright © 2023 Texas Instruments Incorporated
DAC39RF10 device data
Supported by TSW14J59EVM
(1)
L = 1, 2, 3, 4, 6, 8,12,16 supported
Lane rates from 2 to 17.16 Gbps
ƒ
parameter must be properly set in HSDC Pro
(SAMPLE)
www.ti.com
sheet.
Table 4-1
lists
Supported
Not Supported
GUI.
SBAU395 – APRIL 2023
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