Figure 7-2. Ext->Dacclk | Lmx/Lmk-> Fpga Clocking System Block - Texas Instruments DAC39RF10EVM User Manual

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7.1.2 EXT->DACCLK | LMX/LMK-> FPGA Clocking Option
The DAC39RF10EVM can be configured to use EXT->DACCLK | LMX/LMK-> FPGA Clocking option. Similar to
above use case The user provide a single high frequency (10-15 dBm) signal to an SMA labeled LMX CLKp.
This signal is routed though the splitter to Balun and LMX1204. The Balun converts the single ended signal
into differential and is used to clock the DAC. The second output from the splitter is used by LMX1204 which
generates the low frequency DAC SYSERF signal, FPGA reference clocks and FPGA SYSREF signal. The
FPGA reference clocks and FPGA SYSREF signal are feed into the CLKIN1 and CLKIN0 of LMK04828. The
LMK04828 and is used in clock distribution mode and provides several copies/divided down version of FPGA
reference clock and FPGA SYSREF signal.
The EVM can be configured to use onboard clocking option with the following steps:
• Remove C141 and C142, populate C136 and C139
• Remove C138 and C140, populate C134 and C135
• Remove C75 and C76, populate C73 and C74
Spli e r
¡
DEV CLK
10.24GHz
Ext-> DACCLK | LMX/LMK->FPGA
Figure 7-2. EXT->DACCLK | LMX/LMK-> FPGA Clocking System Block Diagram
SBAU395 – APRIL 2023
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Figure 7-2
LMX1204
CLKIN
CLKOUTA
SYSREFREQ SYSREFA
EXT SYSREF
5MHz
LOGIC SYSREF
EXT REF
160MHz
LOGIC CLK
Copyright © 2023 Texas Instruments Incorporated
shows the block diagram of clocking option:
LMK04828
CLKIN0 SDCLKx
n
SDCLKx
n
DCLKx
DCLKx
Appendix
FMC
DAC39RF10
CLK
JESD SYNC JESD SYNC
SYSREF
DA[15:0] DA[15:0]
FPGA SYSREF
FPGA REF CLK
FPGA CORE CLK
DAC39RF10EVM Evaluation Module 21