Figure 7-3. External Reference Clocking System Block Diagram - Texas Instruments DAC39RF10EVM User Manual

Appendix
7.1.3 EXT->DACCLK | LMK-> FPGA Clocking Option
The DAC39RF10EVM can be configured to use EXT->DACCLK | LMK-> FPGA Clocking option. In this use
case, the user provide a two clock signal. A high frequency(10-15dBm) signal to an SMA labeled LMX CLKp.
This signal is routed though the splitter to Balun and LMX1204. The Balun converts the single ended signal into
differential and is used to clock the DAC. The second low frequency signal is CLKIN1 input of LMK04828. The
LMK04828 is used to generates the low frequency DAC SYSERF signal, FPGA reference clocks and FPGA
SYSREF signal. The LMK04828 is used in clock distribution mode and provides several copies/divided down
version of FPGA reference clock and FPGA SYSREF
reference clocking option:
The EVM can be configured to use external reference clocking option with the following steps:
• Remove C141 and C142, populate C136 and C139
• Remove C138 and C140, populate C134 and C135
• Remove C65 and R64, populate C64 and R66
• Remove C73 and C74, populate C75 and C76
Spli e r
¡
DEV CLK
10.24GHz
CLKIN
SYSREFREQ
Ext-> DACCLK | LMK->FPGA

Figure 7-3. External Reference Clocking System Block Diagram

22 DAC39RF10EVM Evaluation Module
LMX1204
CLKOUTA
SYSREFA
EXT SYSREF
5MHz
LOGIC SYSREF
EXT REF
160MHz
LOGIC CLK
Copyright © 2023 Texas Instruments Incorporated
signalFigure 7-3 shows the block diagram of external
LMK04828
CLKIN0 SDCLKx
n
SDCLKx
n
DCLKx
DCLKx
www.ti.com
DAC39RF10 FMC
CLK
JESD SYNC JESD SYNC
SYSREF
DA[15:0] DA[15:0]
FPGA SYSREF
FPGA REF CLK
FPGA CORE CLK
SBAU395 – APRIL 2023
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