Marvell ARMADA 88F6810 Hardware Design Manual page 9

Figure 39: On-Board 32-bit, 2x16-bit Single-Side Assembly Topology with ECC-Data ................................. 63
Figure 40: On-Board 32-bit, 4x8-bit Single-Side Assembly Topology with ECC-Address and Control ......... 66
Figure 41: On-Board 32-bit, 4x8-bit, with ECC, Single-Side Assembly Topology-Data ................................. 67
Figure 42: On-Board 32-bit, 8x8-bit Clamshell Topology with ECC-Address and Control ............................. 70
Figure 43: On-Board 32-bit, 8x8-bit Clamshell Topology with ECC-Data ...................................................... 71
Figure 44: On-Board 32-bit, 4x8-bit Single-Side Connectivity ......................................................................... 77
Figure 45: On-Board 32-bit, 4x8-bit Single-Side Assembly Topology with ECC-Address and Control ......... 80
Figure 46: On-Board 32-bit, 4x8-bit, with ECC, Single-Side Assembly Topology-Data ................................. 81
Figure 47: RGMII Port Connection to PHY ...................................................................................................... 87
Figure 48: RGMII Port Connection to Another RGMII MAC ............................................................................. 87
Figure 49: RGMII Routing Topology ................................................................................................................ 88
Figure 50: SGMII Generic Point-to-Point Connection ...................................................................................... 91
Figure 51: SGMII Topology for Chip-to-Chip, End-to-End Connection ............................................................ 92
Figure 52: SGMII Generic Point-to-Point Connection ...................................................................................... 95
Figure 53: Topology for Chip-to-Chip, End-to-End Connection ....................................................................... 96
Figure 54: QSGMII Generic Point-to-Point Connection ................................................................................... 99
Figure 55: QSGMII Topology for Chip-to-Chip, End-to-End Connection ....................................................... 100
Figure 56: PCI Express Interface Connectivity .............................................................................................. 104
Figure 57: PCI Express Interface Connectivity and Reference Clock Supplied by Marvell
Figure 58: Topology with an Existing Connector and/or an Add-in Card ....................................................... 105
Figure 59: Topology with a Same-Board Connection .................................................................................... 108
Figure 60: PCI Express Interface Connectivity .............................................................................................. 112
Figure 61: PCI Express Interface Connectivity and Reference Clock Supplied by Marvell
Figure 62: Topology with an Existing Connector and/or an Add-in Card ....................................................... 114
Figure 63: Topology with a Same-Board Connection .................................................................................... 117
Figure 64: USB 2.0 Interface Connectivity to a Connector-Including Optional Common Mode Choke and
Protection Diodes Circuitry ...........................................................................................................120
Figure 65: Vbus Connectivity when Configured as a Host ............................................................................. 121
Figure 66: Vbus Connectivity when Configured as a Device ......................................................................... 121
Figure 67: Topology-Including Common Mode Choke and Protection Diodes Optional Circuitry-when
Configured as a Device
Figure 68: Topology-Including Optional Common Mode Choke and Protection Diodes Circuitry-when
Configured as a Host ....................................................................................................................124
Figure 69: Topology-Including Common Mode Choke and Protection Diodes
Optional Circuitry-when Configured as a Device .......................................................................127
Figure 70: Topology-Including Optional Common Mode Choke and Protection
Diodes Circuitry-when Configured as a Host ..............................................................................129
Figure 71: SATA Interface Connectivity ......................................................................................................... 131
Figure 72: Topology for Connection to a Standard SATA 3.0 1-Meter Cable ................................................ 132
Figure 73: SDIO 3.0/MMC4.4 Connection to Connector Side ....................................................................... 134
Figure 74: SDIO 3.0/MMC 4.4 Routing Topology .......................................................................................... 135
Figure 75: Clock Transition Examples ........................................................................................................... 138
Figure 76: Master SMI Connectivity Example ................................................................................................ 138
Figure 77: Using Two 8-bit Flash Devices to Comprise a 16-bit Bus ............................................................. 139
Figure 78: Example of a 16-bit Wide Device Connection .............................................................................. 140
Copyright © 2017 Marvell
August 30, 2017
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Document Classification: Public
List of Figures
®
Device ............. 104
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Device ............. 113
Doc. No. MV-S302310-U0 Rev. A
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