Marvell ARMADA 88F6810 Hardware Design Manual page 10

88F6810, 88F6820 and 88F6828
Hardware Design Guide
Figure 79: Example of a 512 KB Flash Device with an 8-bit Data Bus Connection ....................................... 141
Figure 80: DEV_READYn Connection Example ............................................................................................ 142
Figure 81: Connectivity for Chip Enable Don't Care NAND Flash ................................................................ 143
Figure 82: Core Clock Connectivity ............................................................................................................... 145
Figure 83: Reference Clock Distribution ........................................................................................................ 146
Figure 84: Clock Topology ............................................................................................................................. 147
Figure 85: Internal Reference Clock with up to 2 PCIe Root Complex Ports ................................................. 148
Figure 86: External Reference Clock with 4 PCIe Root Complex Ports ......................................................... 149
Figure 87: External Reference Clock with 1 PCIe Endpoint and 3 Root Complex Ports ............................... 149
Figure 88: Internal Reference Clock Topology with 4 PCIe Root Complex Ports .......................................... 150
Figure 89: Internal Reference Clock Topology with 1 PCIe Endpoint and 3 Root Complex Ports ................. 150
Figure 90: Board Connectivity for VDD_CPU with Direct AVS Feedback Connection ................................. 152
Figure 91: Board Connectivity for VDD_CPU with AVS Feedback Connection with Resistor Voltage
Divider Regulator ..........................................................................................................................152
Doc. No. MV-S302310-U0 Rev. A
Page 3 Document Classification: Public
Copyright © 2017 Marvell
August 30, 2017