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88F6810, 88F6820 and 88F6828
Hardware Design Guide
Table 40: Same-Board Connection (Continued)
P ar a m e te r
TL4 length
(TL3n+TL4n)-(TL3m+TL4m) lane-to-lane skew
C1
Notes:
1. Target impedance should be 85
2. Derived from the loss value by calculation with 0.5 dB/inch.In many cases, the routing is done using
external routing board routing layers (u-strip). In these cases, the loss per inch is usually lower
(around 0.33dB/inch) and the maximal length can be calculated accordingly.
3. Discontinuities, such as capacitive type, can cause significant insertion loss degradation, causing the
assumption, taken as loss per inch, to be smaller than actual.
4. The maximal allowed trace length can vary according to the material and geometrical characteristics.
5. The maximal allowed length or loss is assumed for the same Marvell
different peer device, refer to its design guidelines for TL1+ TL2 allowed loss.
6. The interconnect is not defined for the low voltage swing option, as described in the PCI Express Base
2.0 Specification, Section 4.3.6.2.6. The interconnect defined by TL1+TL2 is meant to account for
long, loss dominant, interconnects with low-reflection dominant, notch-like behavior. For
reflection-dominant interconnects, a simulation should be performed. The simulation procedure is
defined in the PCI Express Base 2.0 Specification, Section 4.3.6.2.1: Procedure for Channel
Measurement and Margin Extraction.
7. m and n are lane numbers in cases of multi-lane interface only (m, n may be 0, 1, 2, 3, etc.).
8. x and y represent lane numbers, or different, same-direction PCIe SERDES differential lines.
9. The separation is calculated assuming the same type of SERDES and typical board layer stack-up.
Make certain to verify that the crosstalk limitation is met in each specific system.
10. The separation value is calculated for a single-ended impedance of 47-ohm, a differential impedance
of 85-ohm, u-strip trace length coupled along the entire end-to-end path, and a dielectric loss
coefficient of 0.027. If the loss coefficient is lower, a higher separation may be required.
11. The allowed crosstalk is highly dependent on the aggressor's waveform (rise time and swing). The
recommended crosstalk value should account for all common aggressor types. The recommended
separation value is for an aggressor of the same type of interface.
12. It is essential to use high-speed, low-ESL, low-ESR capacitors.
Doc. No. MV-S302310-U0 Rev. A
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differential; any mismatch should be taken as a part of the loss.
Document Classification: Public
M a x
Un i ts
N ot e s
0.5
inch
5
inch
3, 4, 7
200
nF
12
®
device on both ends. If using a
Copyright © 2017 Marvell
August 30, 2017
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