Table of Contents
Advertisement
Table 28: Routing Constraints for a Chip-to-Chip End-to-End Connection
P ar a m e te r
TL1[x] or TL3[x] to TL[x] lane
separation from other traces
(crosstalk)
TL1[x] to TL3[y] Tx to Rx separation
(dimensions)
TL1[x] to TL3[y] Tx to Rx separation
(near-end crosstalk)
TL1+TL2, TL3 + TL4 inner-pair
skew
Tn Differential impedance
Tn single-ended impedance
C1
NOTES:
1. Target impedance should be 100Ω differential; any mismatch should be included as a part of the loss.
2. Derived from the loss value by calculation with 0.3 dB/inch.
3. Loss budget is meant for trace loss and should include far-end crosstalk.
4. Re-calculate or simulate to get the maximum allowed trace length for an end-to-end connection that is
not confined to one board. The connector discontinuity effect must be included in the calculation.
5. Refer to the Hardware Specifications for the maximal allowed ISI. For the ISI term definition, refer to
Section 2.2, Inter-Symbol Interference (ISI), on page
6. Discontinuities, such as capacitive type, can cause significant insertion loss degradation, causing the
assumption, taken as loss per inch, to be smaller than actual.
7. The maximal allowed trace length can vary according to the material and geometrical characteristics.
8. The maximal allowed length or loss is assumed for the same Marvell device on both ends. If using a
different peer device, refer to its design guidelines for TL1+ TL2 allowed loss.
9. This value is based on a 2.5-Gb-SGMII-compliant driver on the peer device, with a differential
amplitude of not less than 800 mV.
10. The interconnect loss should have a smooth progression through frequency, with no notch-like
behavior, up to 3.125 GHz (Fbaud).
11. In any case where the end-to-end trace is not confined within the same board, maintain end-to-end
parameters. These parameters include insertion loss and crosstalk over the complete connection,
taking into account connectors and cables.
12. x and y represent lane numbers.
13. The separation is calculated assuming the same type of SERDES and typical board layer stack-up.
Make certain to verify that the crosstalk limitation is met in each specific system.
14. The allowed crosstalk is highly dependant of the aggressor's waveform (rise time and swing). The
recommended separation value should account for all common aggressor types.
15. For BGA packages, some package length routing skew may exist. This helps compensate for ball
position within the pinout.
16. TL1, TL2, TL3, and TL4 length should each be inner-pair lengths matched separately, to allow the
end-to-end, total inner-pair length match.
17. Target impedance priority is to match the differential impedance of these signal traces and adjust the
single-ended impedance accordingly.
18. The tolerance is manufacturing tolerance.
19. The AC coupling capacitors can be omitted, if the peer device supplies AC coupling capacitors inside
the package.
20. It is essential to use high-speed, low-ESL, low-ESR capacitors.
Copyright © 2017 Marvell
August 30, 2017
High Speed Serial Gigabit Media Independent Interface (HS-SGMII)
Min
4
50
10
Document Classification: Public
Interface Signals Layout Guidelines
M a x
To le ra n c e
-40
-40
100
100
±10%
53.5
220
12.
Units
No t es
dB
14
signal
12
width
dB
mil
8, 15, 16
Ω
17, 18
Ω
17
nF
19, 20
Doc. No. MV-S302310-U0 Rev. A
Page 97
Advertisement
Table of Contents
