Marvell ARMADA 88F6810 Hardware Design Manual page 5

6.2 Interface Signals Layout Guidelines .............................................................................................................. 44
6.3 Special Software Setting ............................................................................................................................... 55
7 32-bit SDRAM DDR3 Interface .................................................................................................. 56
7.1 Interface Connectivity .................................................................................................................................... 56
7.2 Interface Signals Layout Guidelines .............................................................................................................. 61
7.3 Power Signals ............................................................................................................................................... 73
7.4 Special Software Setting ............................................................................................................................... 73
8 32-bit SDRAM DDR4 Interface .................................................................................................. 75
8.1 Interface Connectivity .................................................................................................................................... 75
8.2 Interface Signals Layout Guidelines .............................................................................................................. 78
8.3 Power Signals ............................................................................................................................................... 83
8.4 Special Software Setting ............................................................................................................................... 84
9 Network Ethernet Ports ............................................................................................................. 85
10 Reduced Gigabit Media Independent Interface (RGMII) ......................................................... 86
10.1 Interface Connectivity .................................................................................................................................... 86
10.2 Connectivity ................................................................................................................................................... 86
10.3 Interface Signals Layout Guidelines .............................................................................................................. 87
11 Serial Gigabit Media Independent Interface (SGMII) ............................................................. 91
11.1 Interface Connectivity .................................................................................................................................... 91
11.2 Interface Signals Layout Guidelines for Chip-to-Chip End-to-End Connection ............................................. 92
11.3 Power Considerations ................................................................................................................................... 94
11.4 Specific Signals ............................................................................................................................................. 94
12 High Speed Serial Gigabit Media Independent Interface (HS-SGMII) ................................... 95
12.1 Interface Connectivity .................................................................................................................................... 95
12.2 Interface Signals Layout Guidelines .............................................................................................................. 96
12.3 Power Considerations ................................................................................................................................... 98
12.4 Specific Signals ............................................................................................................................................. 98
13 Quad Serial Gigabit Media Independent Interface (QSGMII) ................................................ 99
13.1 Interface Connectivity .................................................................................................................................... 99
13.2 Interface Signals Layout Guidelines for Chip-to-Chip End-to-End Connection ........................................... 100
13.3 Clock Considerations .................................................................................................................................. 102
13.4 Power Considerations ................................................................................................................................. 102
13.5 Specific Signals ........................................................................................................................................... 102
14 PCI Express (PCIe) Interface 1.0/1.1 ..................................................................................... 103
14.1 Connectivity ................................................................................................................................................. 103
14.2 Interface Signals Layout Guidelines ............................................................................................................ 105
Copyright © 2017 Marvell
August 30, 2017 Document Classification: Public
Table of Contents
Doc. No. MV-S302310-U0 Rev. A
Page 2