Marvell ARMADA 88F6810 Hardware Design Manual page 6

88F6810, 88F6820 and 88F6828
Hardware Design Guide
14.3 Power Considerations ................................................................................................................................. 109
14.4 Specific Signals .......................................................................................................................................... 109
15 PCI Express (PCIe) Interface 2.0 ........................................................................................... 111
15.1 Connectivity ................................................................................................................................................. 111
15.2 Interface Signals Layout Guidelines ............................................................................................................ 113
15.3 Power Considerations ................................................................................................................................. 119
15.4 Reference Clock Considerations ................................................................................................................. 119
15.5 Specific Signals .......................................................................................................................................... 119
16 Universal Serial Bus (USB) 2.0 Interface .............................................................................. 120
16.1 Interface Connectivity .................................................................................................................................. 120
16.2 Interface Signals Layout Guidelines ............................................................................................................ 122
16.3 Power Considerations ................................................................................................................................. 125
16.4 Specific Signals ........................................................................................................................................... 125
17 Universal Serial Bus (USB) 3.0 Interface .............................................................................. 126
17.1 General Design Considerations .................................................................................................................. 126
17.2 Interface Connectivity .................................................................................................................................. 126
18 Serial ATA (SATA) Interface 3.0 ............................................................................................. 131
18.1 Connectivity ................................................................................................................................................. 131
18.2 Interface Signals Layout Guidelines ............................................................................................................ 131
18.3 Clock Considerations .................................................................................................................................. 133
18.4 Power Considerations ................................................................................................................................. 133
18.5 Specific Signals ........................................................................................................................................... 133
19 SDIO 3.0 and MMC 4.4 ............................................................................................................. 134
19.1 Interface Connectivity .................................................................................................................................. 134
19.2 Connectivity ................................................................................................................................................. 134
20 Serial Management Interface (SMI) ....................................................................................... 137
20.1 Interface Connectivity .................................................................................................................................. 137
20.2 Interface Signals Layout Guidelines ............................................................................................................ 137
21 Device Bus Interface ............................................................................................................... 139
21.1 Device Bus Interface Connectivity .............................................................................................................. 139
21.2 DEV_READYn Support ............................................................................................................................... 142
21.3 Device Bus Interface Control Signals at Reset ........................................................................................... 142
21.4 NAND Flash Support ................................................................................................................................... 143
22 General Clock Guidelines ...................................................................................................... 144
22.1 Core Clock .................................................................................................................................................. 145
Doc. No. MV-S302310-U0 Rev. A
Page 3 Document Classification: Public
Copyright © 2017 Marvell
August 30, 2017