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Table 26: Routing Constraints Chip-to-Chip, End-to-End Connection (Continued)
P ar a m e te r
TL1[x] to TL1[y] separation (far-end
crosstalk)
TL1[x] or TL3[x] to TL[x] separation
from other signals (crosstalk)
TL1[x] to TL3[y] Tx to Rx separation
(dimensions)
TL1[x] to TL3[y] Tx to Rx separation
(near-end crosstalk)
TL1+TL2, TL3 + TL4 inner pair skew
Tn Differential impedance
Tn single-ended impedance
C1
NOTES:
1. Target impedance should be 100Ω differential; any mismatch should be taken as a part of the loss.
2. Derived from the loss value by calculation with 0.2 dB/inch @ Fbaud/2.
3. Loss budget is meant for trace loss and should include far-end crosstalk.
4. Re-calculate or simulate to get the maximum allowed trace length for an end-to-end connection that is
not confined to one board. The connector discontinuity effect must be included in the calculation.
5. Refer to the Hardware Specifications for the maximal allowed ISI. For the ISI term definition, refer to
Section 2.2, Inter-Symbol Interference (ISI), on page
6. Discontinuities, such as capacitive type, can cause significant insertion loss degradation, causing the
assumption, taken as loss per inch, to be smaller than actual.
7. The maximal allowed trace length can vary according to the material and geometrical characteristics.
8. The maximal allowed length or loss is assumed for the same Marvell
different peer device, refer to its design guidelines for TL1+ TL2 allowed loss.
9. The interconnect loss should have a smooth progress through frequency, with no notch-like behavior
up to 2 GHz.
10. In any case where the end-to-end trace is not confined within the same board, maintain end-to-end
parameters including insertion loss and crosstalk over the complete connection including connectors,
cables.
11. x and y represent lane or port numbers.
12. The separation is calculated assuming the same type of SERDES.
Make certain to verify that the crosstalk limitation is met in each specific system.
13. The separation is calculated assuming a typical board layer stack-up.
Make certain to verify that the crosstalk limitation is met in each specific system.
14. The allowed crosstalk is highly dependent on the aggressor's waveform (rise time and swing). The
recommended separation value should account for all common aggressor types.
15. For BGA packages some package length routing skew may exist. This helps compensate for ball
position within the pinout.
16. Target impedance priority is to match the differential impedance of these signal traces and adjust the
single-ended impedance accordingly
17. The tolerance is manufacturing tolerance. Keep design impedance tolerance to a minimum. When
compromising differential impedance, lower the characteristic impedance is preferred over an
impedance that exceeds the nominal.
18. The maximum trace single-ended characteristic impedance can be up to 60 ohm, given that the total
trace length is up to 10 inches and includes no connectors.
Copyright © 2017 Marvell
August 30, 2017
Serial Gigabit Media Independent Interface (SGMII)
Interface Signals Layout Guidelines for Chip-to-Chip End-to-End Connection
M i n
3.5
50
10
Document Classification: Public
M a x
To le ra n c e
-26
-40
-40
75
100
±10%
53.5
220
12.
®
device on both ends. If using a
Units
N ot e s
dB
dB
11, 13, 14
signal
11, 12, 13
width
dB
mil
15
ohm
16, 17
ohm
16,18
nF
19, 20, 21
Doc. No. MV-S302310-U0 Rev. A
Page 93
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