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88F6810, 88F6820 and 88F6828
Hardware Design Guide
Table 14: Routing Constraints—On-Board 32-bit with or without ECC, 8x8-bit
P ar a m e te r
TL1+TL11, TL2+TL21 length (stripline)
TL11, TL21 length
byte skew
max(TL1,TL2)-min(TL1,TL2)
DM to DQS skew
TL2-TL1(DM)
Differential in-pair skew:
TL2+TL21
TL3+TL31
TL3+TL32+TL31
TL3+TL32+TL33+...+TL31
DQS to Clock skew:
(TL3+TL31)–(TL2+TL21)
(TL3+TL32+TL31)–(TL2+TL21)
(TL3+TL32+TL33+...+TL31)–
(TL2+TL21)
Address/Command to Clock skew:
(TL3+TL31)-(TL4+TL41)
(TL3+TL32+TL31)–(TL4+TL42+TL41)
(TL3+TL32+TL33+...+TL31)–
(TL4+TL42+TL43+...+TL41)
Control to Clock skew:
(TL3+TL31)–(TL5+TL51)
(TL3+TL32+TL31)–(TL5+TL52+TL51)
(TL3+TL32+TL33+...+TL31)–
(TL5+TL52+TL53+...+TL51)
TL31,TL41, TL51
TL32, TL34, TL35 length
TL42, TL44, TL45 length
TL52, TL54, TL55 length
TL33, TL43, TL53 length
Clock length to last device:
TL3+TL32+TL33+...+TL31 length
TL7 length
R1
TL[x] impedance (all other
single-ended traces)
TL2, TL3 differential impedance
TL2, TL3 single-ended impedance
NOTES:
1. If the design cannot meet the above requirements for length and separation, simulation should be
performed to ensure proper isolation between signals.
2. The separation is defined from edge-to-edge of two traces.
Doc. No. MV-S302310-U0 Rev. A
Page 72
Clamshell Topology (Continued)
Document Classification: Public
Min
M a x
To l e r a n c e
/ Skew
700
100
500
-50
50
-10
10
0
-0.5
0.5
-0.5
0.5
100
0.5
1.3
0.5
1.8
8
0.5
36
39
5%
45
55
10%
100
10%
60
10%
U ni ts
N ot e s
mil
3, 5
mil
mil
mil
mil
inch
6
inch
7
inch
mil
inch
inch
inch
inch
ohm
8, 9
ohm
11
ohm
10, 12
ohm
10, 12
Copyright © 2017 Marvell
August 30, 2017
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