Marvell ARMADA 88F6810 Hardware Design Manual page 11

List of Tables
Table 1: Revision History ................................................................................................................................ 3
Table 1: Related Documents .......................................................................................................................... 3
Table 2: 4-Layer Stack Up Example ............................................................................................................... 5
Table 3: List of Capacitors .............................................................................................................................. 8
Table 4: Definition of Analog Power Filter Symbols ...................................................................................... 33
Table 5: Signal Groups ................................................................................................................................. 40
Table 6: Routing Constraints when Using On Board 16-bit, 1x16-bit Wide Memory Topology -
Address and Control Using a Clamshell Assembly .........................................................................46
Table 7: Routing Constraints-On-Board 16-bit, 2x8-bit Topology ............................................................... 50
Table 8: Routing Constraints when Using On Board 16-bit, 4x8-bit Wide Memory Topology Using a
Clamshell Assembly .......................................................................................................................53
Table 9: ODT Control Matrix for SDRAM DDR3 with 1 Chip Select ............................................................. 55
Table 10: ODT Control Matrix for SDRAM DDR3 with 2 Chip Selects Using a Clamshell Assembly ............. 55
Table 11: Signal Groups ................................................................................................................................. 56
Table 12: Routing Constraints-32-bit, 2x16-bit Single Side Assembly Topology ......................................... 63
Table 13: Routing Constraints-On-Board 32-bit with or without ECC, 4x8-bit Topology .............................. 68
Table 14: Routing Constraints-On-Board 32-bit with or without ECC, 8x8-bit Clamshell Topology ............. 71
Table 15: ODT Control Matrix for SDRAM DDR3 with 1 Chip Select ............................................................. 73
Table 16: ODT Control Matrix for SDRAM DDR3 with 2 Chip Selects Using a Clamshell Assembly ............. 74
Table 17: Signal Groups ................................................................................................................................. 75
Table 18: Routing Constraints-On-Board 32-bit with or without ECC, 4x8-bit Topology .............................. 82
Table 19: ODT Control Matrix for SDRAM DDR4 with 1 Chip Select ............................................................. 84
Table 20: Signal Groups ................................................................................................................................. 86
Table 21: No Internal Delay on Transmitting or on Receiving Peer Side-Tx Path ........................................ 88
Table 22: Internal Delay on Transmitting or on Receiving Peer Side-Tx Path ............................................. 89
Table 23: No Internal Delay on Receiving or on Transmitting Peer Side-Rx Path ....................................... 89
Table 24: Internal Delay on Receiving or on Transmitting Peer Side-Rx Path ............................................. 90
Table 25: Signal Groups ................................................................................................................................. 91
Table 26: Routing Constraints Chip-to-Chip, End-to-End Connection ............................................................ 92
Table 27: Signal Groups ................................................................................................................................. 95
Table 28: Routing Constraints for a Chip-to-Chip End-to-End Connection ..................................................... 96
Table 29: Signal Groups ................................................................................................................................. 99
Table 30: Routing Constraints for a Chip-to-Chip End-to-End Connection Topology ................................... 100
Table 31: Signal Groups ............................................................................................................................... 103
Table 32: Specific Device ............................................................................................................................ 103
Table 33: System Board with Existing Connector ......................................................................................... 106
Table 34: Add-in Card ................................................................................................................................... 107
Table 35: Same-Board Connection .............................................................................................................. 108
Table 36: Signal Groups ............................................................................................................................... 111
Table 37: Specific Device ............................................................................................................................. 111
Copyright © 2017 Marvell
August 30, 2017 Document Classification: Public
List of Tables
Doc. No. MV-S302310-U0 Rev. A
Page 1