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Table 13: Routing Constraints—On-Board 32-bit with or without ECC, 4x8-bit
P ar a m e te r
TL2, TL3 differential impedance
TL2, TL3 single-ended impedance
NOTES:
1. If the design cannot meet the above requirements for length and separation, simulation should be
performed to ensure proper isolation between signals.
2. The separation is defined from edge-to-edge of two traces.
3. A typical board dimension example is a 6 mil trace width, and a 12 mil edge-to-edge separation for a
micro strip with 4 mils separation to the nearest reference plane.
4. Separation is required between any signals that are not in the same group, or sub-group.
5. Via crosstalk has a major influence on the total jitter. When signals are routed as micro-strip with no
vias (i.e. Marvell device and SDRAM device are both located on the same layer) the length may be
extended up to 950 mils. When signals are routed as stripline traces with vias between two close
layers (shorter vias), for example from layer 1 to layer 3, the trace length may be extended up to 1.1
inch. Refer to the board recommendation section for the correct breakout methodology for stripline
routing.
6. DQS needs to be equal to or shorter than the Clock to allow the leveling algorithm to work properly.
7. If the design cannot meet this requirement, address/command 2T mode must be activated, lowering
total DRAM performance. The control signals must still meet this requirement.
8. R1 is connected to a VTT power source. The VTT power source should have a nominal voltage of half
of the power rail voltage +/-40 mV.
9. R1 may be replaced by two 70–80 ohm, 1% resistors (of the same value) connected as Thevenin
termination. In this case, the trace length connecting the Thevenin termination resistors should be less
than 100 mils.
10. The tolerance for the matched impedance value is the manufacturing tolerance. The design tolerance
should be kept to a minimum.
11. The target impedance priority is to match the differential impedance of these signal traces and adjust
the single-ended impedance accordingly.
Copyright © 2017 Marvell
August 30, 2017
Topology (Continued)
Document Classification: Public
32-bit SDRAM DDR3 Interface
Interface Signals Layout Guidelines
Min
M a x
To l e r a n c e
/ Skew
100
10%
60
10%
Un it s
No tes
ohm
10, 11
ohm
10, 11
Doc. No. MV-S302310-U0 Rev. A
Page 69
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