Marvell ARMADA 88F6810 Hardware Design Manual page 8

88F6810, 88F6820 and 88F6828
Hardware Design Guide
List of Figures
Figure 1: Insertion Loss Curve ....................................................................................................................... 10
Figure 2: Typical Trace Differential Amplitude Insertion Loss and ISI ........................................................... 12
Figure 3: Difference in Attenuation Due To ISI - Time Domain Influence ...................................................... 13
Figure 4: ISI Originated Jitter - Eye Pattern ................................................................................................... 13
Figure 5: Stack-up Cross-section with a High Probability of Crosstalk .......................................................... 17
Figure 6: Non-continuous Reference Plane Return Current Path Influence .................................................. 19
Figure 7: Layer Transfer ................................................................................................................................ 19
Figure 8: Reference Plane Clearance ............................................................................................................ 21
Figure 9: Changed Width for Differential Impedance Compensation ............................................................. 22
Figure 10: Voids Underneath AC Coupling Capacitors' Pads .......................................................................... 23
Figure 11: Voids Underneath BGA Device Ball ............................................................................................... 24
Figure 12: Voids Underneath SMT Connector/QFP Lead Frame Pads ........................................................... 24
Figure 13: Proper Deskew ............................................................................................................................... 25
Figure 14: Via Structures ................................................................................................................................. 26
Figure 15: Via Stubs ........................................................................................................................................ 27
Figure 16: Differential Via Structure ................................................................................................................. 27
Figure 17: Recommended Via Structure Dimensions for SERDES Interface up to 12.5 Gbps ....................... 28
Figure 18: Recommended Via Structure Dimensions for 25 Gbps SERDES Interfaces .................................. 29
Figure 19: Coupling of Vias .............................................................................................................................. 31
Figure 20: Routing Length Between the Capacitor and the Vias ..................................................................... 31
Figure 21: Required Analog Power Filter Voltage Transfer Function ............................................................... 32
Figure 22: Analog Power Filter Example ......................................................................................................... 33
Figure 23: Return Path Discontinuity-Bypass Capacitor ............................................................................... 35
Figure 24: Placement of a Bypass Capacitor in Relation to Device Ground Pins ............................................ 35
Figure 25: JTAG Connection ........................................................................................................................... 38
Figure 26: On Board 1x16-bit Wide Memory Device with ECC Connected to the Controller ........................... 41
Figure 27: On Board 2x8-bit Wide Memory Devices with ECC Connected to the Controller ........................... 42
Figure 28: On Board 16-bit, 4x8-bit Wide Memory Devices with ECC Connected to the Controller ................ 43
Figure 29: On Board 16-bit, 1x16-bit Wide Memory with ECC Topology-Address and Control .................... 45
Figure 30: On Board 16-bit, 1x16-bit Single-Side Assembly Topology with ECC-Data ................................. 46
Figure 31: On Board 16-bit, 2x8-bit Wide Memory Topology with ECC -Address
and Control in Daisy Chain .............................................................................................................48
Figure 32: On-Board 16-bit, 2x8-bit with ECC, Single-Side Assembly Topology-Data .................................. 49
Figure 33: On Board 16-bit, 4x8-bit Wide Memory Topology for Clock/Address/Command/Control with
ECC Implemented as a Clamshell Assembly .................................................................................52
Figure 34: On Board 16-bit, 4x8-bit Wide Memory with ECC Topology for Data ............................................. 53
Figure 35: On-Board 32-bit 2 Memory Devices, 2x16-bit Single-Side Connectivity ......................................... 58
Figure 36: On-Board 32-bit, 4x8-bit Single-Side Connectivity ......................................................................... 59
Figure 37: On-Board 32-bit, 8x8-bit Clamshell Connectivity with ECC ............................................................ 60
Figure 38: On-Board 32-bit, 2x16-bit Single-Side Assembly Topology-Address and Control with ECC ....... 62
Doc. No. MV-S302310-U0 Rev. A
Page 1 Document Classification: Public
Copyright © 2017 Marvell
August 30, 2017