32-Bit Sdram Ddr3 Interface; Interface Connectivity; Table 11: Signal Groups - Marvell ARMADA 88F6810 Hardware Design Manual

88F6810, 88F6820 and 88F6828
Hardware Design Guide
7

32-bit SDRAM DDR3 Interface

The design guidelines presented in this section are relevant for the following SDRAM DDR3 32-bit
interface configurations:
2 memory devices with or without ECC support, each with 16-bit wide on-board single side

assembly
4 memory devices with or without ECC support, each with 8-bit wide on-board single side

assembly
8 memory devices with or without ECC support, each with 8-bit wide on-board clamshell

assembly
Note
7.1

Interface Connectivity

The DDR3 SDRAM interface of the Marvell
standard JESD79-3. This section describes the signals of this interface, their role, and how the
signals connect to SDRAM devices.
Section 7.1.1, Signal Groups

Section 7.1.2, Connectivity with 1 Chip Select 32-bit, 2x16-bit Wide Memory with or without

ECC
Section 7.1.3, Connectivity with 1 Chip Select 32-bit, 4x8-bit Wide Memory with or without ECC

Section 7.1.4, Connectivity with 2 Chip Selects 32-bit, 8x8-bit Wide Memory with or without

ECC Using A Clamshell Assembly
7.1.1 Signal Groups
Table 11 lists the signal groups and indicates which signals are differential pairs.
.

Table 11: Signal Groups

G r o u p N a m e
Byte[0]
Byte[1]
Doc. No. MV-S302310-U0 Rev. A
Page 56
These design guidelines are restricted to DDR3 interfaces, operating at voltage values
specified in the device Hardware Specifications and working at frequency up to
800 MHz (DDR3-1600)
S u b G r ou p
N a m e
Data[7:0]
Data Strobe[0]
Data[15:8]
Data Strobe[1]
Document Classification: Public
®
device complies with the DDR3 SDRAM JEDEC
®
M a r ve l l D e v i c e
S ig n a l
DQ[7:0], DM[0]
DQS/DQSn[0]
DQ[15:8], DM[1]
DQS/DQSn[1]
C o m m e n t s
Differential pair
Differential pair
Copyright © 2017 Marvell
August 30, 2017