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Table 30: Routing Constraints for a Chip-to-Chip End-to-End Connection Topology
P ar a m e te r
TL3 + TL4 length
TL3 + TL4 loss @ 2.5 GHz
TL3 + TL4 loss @ 5 GHz
TL1[x] to TL3[y] Tx to Rx
separation (dimensions)
TL1[x] to TL3[y] Tx to Rx
separation (near-end crosstalk)
TL1+TL2, TL3 + TL4 inner-pair
skew
Tn differential impedance
Tn single-ended impedance
C1
NOTES:
1. Target impedance should be 100 ohm differential; any mismatch should be taken as a part of the loss.
2. Derived from the loss value by calculation with 0.5 dB/inch @ Fbaud/2.
3. Loss budget is meant for trace loss and should include far-end crosstalk.
4. Re-calculate or simulate to get the maximum allowed trace length for an end-to-end connection that is
not confined to one board. The connector discontinuity effect must be included in the calculation.
5. Refer to the Hardware Specifications for the maximal allowed ISI. For the ISI term definition, refer to
Section 2.2, Inter-Symbol Interference (ISI), on page
6. Discontinuities, such as capacitive type, can cause significant insertion loss degradation, causing the
assumption, taken as loss per inch, to be smaller than actual.
7. The maximal allowed trace length can vary according to the material and geometrical characteristics.
8. The maximal allowed length or loss is assumed for the same Marvell
different peer device, refer to its design guidelines for TL1+ TL2 allowed loss.
9. The interconnect loss should have a smooth progression through frequency with no notch-like
behavior up to 5 GHz
10. In any case where the end-to-end trace is not confined within the same board, maintain end-to-end
parameters, including insertion loss and crosstalk over the complete connection. Take into
consideration connectors and cables.
11. The separation is calculated assuming the same type of SERDES.
12. x and y represent lane numbers.
13. The allowed crosstalk is highly dependent on the aggressor's waveform (rise time and swing). The
recommended separation value should account for all common aggressor types.
14. For BGA packages, some package length routing skew may exist. This helps compensate for ball
position within the pinout.
15. Target impedance priority is to match the differential impedance of these signal traces and adjust the
single-ended impedance accordingly.
16. The tolerance is manufacturing tolerance.
17. AC coupling is mandatory to allow interoperability between devices with different common mode
voltages including connecting two Marvell
18. The capacitor must be a high-speed, low-ESL, low-ESR type capacitor.
Copyright © 2017 Marvell
August 30, 2017
Quad Serial Gigabit Media Independent Interface (QSGMII)
Interface Signals Layout Guidelines for Chip-to-Chip End-to-End Connection
(Continued)
M in
5
50
10
Document Classification: Public
M ax
Tol e ra n c e
13
6.6
13.5
-40
50
100
±10%
53.5
220
12.
®
®
devices.
Units
No tes
inch
1, 2, 3, 4, 6,
7
dB
3, 12, 9
dB
3, 12, 9
signal
12
width
dB
mil
14
ohm
15, 16
ohm
15
nF
17, 18
device on both ends. If using a
Doc. No. MV-S302310-U0 Rev. A
Page 101
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