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Table 38: System Board with Existing Connector (Continued)
P ar a m e te r
(TL1n+TL2n)-(TL1m+TL2m) lane-to-lane skew
(TL3n-TL3m) lane-to-lane skew
TL1+TL2, TL3 inner pair skew
TL1, TL2, and T3 single-ended impedance
TL1, TL2 and TL3 differential impedance
C1
NOTES:
1. Target impedance should be 85
2. Derived from the loss value by calculation with 0.5 dB/inch. In many cases, the routing is done using
external routing layers (u-strip). In these cases, the loss per inch is usually lower (around 0.33dB/inch)
and the maximal length can be calculated accordingly.
3. The maximal value allowed when using a 6 dB de-emphasis. For shorter traces, it is possible to use a
3.5 dB de-emphasis.
4. Discontinuities, such as capacitive type, can cause significant insertion loss degradation, causing the
assumption, taken as loss per inch, to be smaller than actual.
5. The maximal allowed trace length can vary according to the material and geometrical characteristics.
6. The interconnect is not defined for the low voltage swing option, as described in the PCI Express Base
2.0 Specification . The interconnect defined by TL1+TL2 is meant to account for long, loss dominant,
interconnects with a low-reflection dominant, notch-like behavior. For reflection-dominant
interconnects, a simulation must be performed. The simulation procedure is defined in the PCI
Express Base 2.0 Specification procedure for channel measurement and margin extraction.
7. x and y represent lane numbers, or different, same-direction PCIe SERDES differential lines.
8. The separation is calculated assuming the same type of SERDES and typical board layer stack-up.
Make certain to verify that the crosstalk limitation is met in each specific system.
9. The separation value is calculated for a single-ended impedance of 47-ohm, a differential impedance
of 85-ohm, u-strip trace length coupled along the entire end-to-end path, and a dielectric loss
coefficient of 0.027. If the loss coefficient is lower, a higher separation may be required.
10. The allowed crosstalk is highly dependent on the aggressor's waveform (rise time and swing). The
recommended crosstalk value should account for all common aggressor types. The recommended
separation value is for an aggressor of the same type of interface.
11. m and n are lane numbers in cases of multi-lane interface only (m, n may be 0, 1, 2, 3, etc.)
12. Derived from 1.25 ns lane-to-lane skew specification in the in the PCI Express Card
Electromechanical 2.0 Specification.
13. In cases of BGA packages, some package length routing skew can be present. This skew can help
compensate for pin position within the pinout. Refer to the device's hardware specifications for specific
package trace length information.
14. It is essential to use high-speed, low-ESL, low-ESR capacitors.
Copyright © 2017 Marvell
August 30, 2017
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differential; any mismatch should be taken as a part of the loss.
Document Classification: Public
PCI Express (PCIe) Interface 2.0
Interface Signals Layout Guidelines
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