Chop Enabled (Sinc Filter) - Analog Devices AD7195 Manual

AD7195
CHOP ENABLED (SINC
With chop enabled, the ADC offset and offset drift are
minimized. The analog input pins are continuously swapped.
With the analog input pins connected in one direction, the
settling time of the sinc filter is allowed and a conversion is
recorded. The analog input pins invert and another settled
conversion is obtained. Subsequent conversions are averaged
to minimize the offset. This continuous swapping of the analog
input pins and the averaging of subsequent conversions means
that the offset drift is also minimized. With chop enabled, the
resolution increases by 0.5 bits. Using the sinc
enabled is suitable for output data rates up to 320 Hz.
CHOP
Figure 45. Chop Enabled (Sinc
Output Data Rate and Settling Time (Sinc
Enabled)
3
For the sinc filter, the output data rate is equal to
f = f /(3 × 1024 × FS[9:0])
ADC CLK
where:
f is the output data rate.
ADC
f is the master clock (4.92 MHz nominal).
CLK
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The value of FS[9:0] can be varied from 1 to 1023. This results
in an output data rate of 1.56 Hz to 1600 Hz. The settling time
is equal to
t = 2/f
SETTLE ADC
Table 34. Examples of Output Data Rates and the
Corresponding Settling Time (Chop Enabled, Sinc
FS[9:0] Output Data Rate (Hz)
96 16.7
80 20
When a channel change occurs, the modulator and filter are
reset. The complete settling time is required to generate the first
conversion after the channel change. Subsequent conversions on
this channel occur at 1/f
CHANNEL A
CHANNEL
CONVERSIONS
CH A CH A CH A
Figure 46. Channel Change (Sinc
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3
FILTER)
3
filter with chop
ADC
3 4
MODULATOR SINC /SINC
3
Chop Enabled)
3
Chop
3
Filter)
Settling Time (ms)
120
100
.
ADC
CHANNEL B
CH B CH B CH B CH B
f
1/
ADC
3
Chop Enable)
If conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in analog
input; therefore, it continues to output conversions at the
programmed output data rate. However, it is at least two
conversions later before the output data accurately reflects
the analog input. If the step change occurs while the ADC is
processing a conversion, then the ADC takes three conversions
after the step change to generate a fully settled result.
ANALOG
INPUT
ADC
OUTPUT
Figure 47. Asynchronous Step Change in Analog Input (Sinc
The cutoff frequency f
f = 0.24 × f
3dB
50 Hz/60 Hz Rejection (Sinc
When FS[9:0] is set to 96 and chopping is enabled, the filter
response shown in Figure 48 is obtained. The output data rate
is equal to 16.7 Hz for a 4.92 MHz master clock. The chopping
introduces notches at odd integer multiples of f
notches due to the sinc filter in addtion to the notches intro-
duced by the chopping means that simultaneous 50 Hz and
60 Hz rejection is achieved for an output data rate of 16.7 Hz.
The rejection at 50 Hz/60 Hz ± 1 Hz is typically 53 dB,
assuming a stable master clock.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
Figure 48. Sinc
CH B
Rev. 0 | Page 40 of 44
FULLY
SETTLED
f
1/
ADC
is equal to
3dB
ADC
3
Chop Enabled)
ADC
25 50 75 100
FREQUENCY (Hz)
3
Filter Response (FS[9:0] = 96, Chop Enabled)
3
Chop Enabled)
/2. The
125 150