Sinc 3 Filter (Chop Disabled) - Analog Devices AD7195 Manual

AD7195
The output data rate is 50 Hz when zero latency is disabled and
12.5 Hz when zero latency is enabled. Figure 31 shows the
frequency response of the sinc
±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming
a stable 4.92 MHz master clock.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 25
4
Figure 31. Sinc
3
SINC FILTER (CHOP DISABLED)
3
A sinc filter can be used instead of the sinc
selected using the SINC3 bit in the mode register. The sinc
filter is selected when the SINC3 bit is set to 1.
This filter has good noise performance when operating with
output data rates up to 1 kHz. It has moderate settling time and
moderate 50 Hz/60 Hz (±1 Hz) rejection.
CHOP
Figure 32. Sinc
Sinc 3 Output Data Rate and Settling Time
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
f = f /(1024 × FS[9:0])
ADC CLK
where:
f is the output data rate.
ADC
f is the master clock (4.92 MHz nominal).
CLK
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time is equal to
t = 3/f
SETTLE ADC
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4
filter. The filter provides 50 Hz
50 75 100 125
FREQUENCY (Hz)
Filter Response (FS[9:0] = 96, REJ60 = 1)
4
filter. The filter is
ADC
3 4
MODULATOR SINC /SINC
3
Filter (Chop Disabled)
The 3 dB frequency is equal to
f = 0.272 × f
3dB
Table 31 gives some examples of FS settings and the corres-
ponding output data rates and settling times.
Table 31. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0] Output Data Rate (Hz)
480 10
96 50
80 60
When a channel change occurs, the modulator and filter reset.
The complete settling time is allowed to generate the first
conversion after the channel change (see Figure 33). Subsequent
conversions on this channel are available at 1/f
CHANNEL
150
CONVERSIONS
When conversions are performed on a single channel and a step
3
change occurs, the ADC does not detect the change in analog
input. Therefore, it continues to output conversions at the program-
med output data rate. However, it is at least three conversions later
before the output data accurately reflects the analog input. If the
step change occurs while the ADC is processing a conversion, the
ADC takes four conversions after the step change to generate a fully
settled result.
ANALOG
INPUT
ADC
OUTPUT
Figure 34. Asynchronous Step Change in Analog Input
3
Sinc Zero Latency
Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
is allowed for each conversion. Therefore, the conversion time
when converting on a single channel or when converting on
several channels is constant. The user does not need to consider
the effects of channel changes on the output data rate.
Rev. 0 | Page 36 of 44
ADC
Settling Time (ms)
300
60
50
CHANNEL B
CHANNEL A
CH A CH A CH A CH B
f
1/
ADC
3
Figure 33. Sinc Channel Change
f
1/
ADC
.
ADC
CH B CH B CH B
FULLY
SETTLED