Analog Devices AD7195 Manual page 5

Parameter
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
2
Hysteresis
Input Currents
LOGIC OUTPUT (DOUT/ RDY )
Output High Voltage, V
Output Low Voltage, V
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage
Current
Floating-State Output
Capacitance
Data Output Coding
SYSTEM CALIBRATION
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
POWER REQUIREMENTS
Power Supply Voltage
AV − AGND
DD
DV − DGND
DD
Power Supply Currents
AI Current
DD
DI Current
DD
I (Power-Down Mode)
DD
1
Temperature range: −40°C to +105°C.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
4
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5 The analog inputs are configured for differential mode.
6
REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.
7
Digital inputs equal to DV
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Min Typ
2
2
INH
2
INL
0.1
−10
2
DV − 0.6
OH DD
2
OL
2
4
OH
2
OL
−10
10
Offset binary
2
−1.05 × FS
0.8 × FS
7
4.75
2.7
0.85
1.1
3.5
4
5
5.5
0.35
0.5
1.5
or DGND.
DD
Max Unit
V
0.8 V
0.25 V
+10 μA
V
0.4 V
V
0.4 V
+10 μA
pF
1.05 × FS V
V
2.1 × FS V
5.25 V
5.25 V
1 mA
1.3 mA
4.5 mA
5 mA
6.4 mA
6.9 mA
0.4 mA
0.6 mA
mA
2 μA
Rev. 0 | Page 5 of 44
1
Test Conditions/Comments
DV = 3 V, I = 100 μA
DD SOURCE
DV = 3 V, I = 100 μA
DD SINK
DV = 5 V, I = 200 μA
DD SOURCE
DV = 5 V, I = 1.6 mA
DD SINK
gain = 1, buffer off
gain = 1, buffer on
gain = 8, buffer off
gain = 8, buffer on
gain = 16 to 128, buffer off
gain = 16 to 128, buffer on
DV = 3 V
DD
DV = 5 V
DD
External crystal used
AD7195