On-Chip Registers - Analog Devices AD7195 Manual

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip registers described on the following pages. In the following descriptions,
the term set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted.
Table 18. Register Summary
Register
Communications
Status
Mode
Configuration
Data
ID
GPOCON
Offset
Full Scale
Downloaded from Elcodis.com electronic components distributor
Addr. Dir. Default Bit 7
00 W 00 WEN
00 R 80 RDY
01 R/W 080060
SINC3
FS7
02 R/W 000117 Chop (MSB)
CH7
BURN
03 R 000000 D23 (MSB)
D15
D7
04 R A6 1
05 R/W 00 0
06 R/W 800000 OF23 (MSB)
OF15
OF7
07 R/W 5XXXX0 FS23 (MSB)
FS15
FS7
Bit 6 Bit 5 Bit 4
R/W Register address
ERR NOREF PARITY
Mode select DAT_STA
0 ENPAR 0
FS6 FS5 FS4
ACX 0 0
CH6 CH5 CH4
REFDET 0 BUF
D22 D21 D20
D14 D13 D12
D6 D5 D4
0 1 0
BPDSW 0 0
OF22 OF21 OF20
OF14 OF13 OF12
OF6 OF5 OF4
FS22 FS21 FS20
FS14 FS13 FS12
FS6 FS5 FS4
Rev. 0 | Page 17 of 44
AD7195
Bit 3 Bit 2 Bit 1 Bit 0
CREAD 0 0
0 CHD2 CHD1 CHD0
CLK1 CLK0 0 0
SINGLE REJ60 FS9 FS8
FS3 FS2 FS1 FS0 (LSB)
0 0 0 0
CH3 CH2 CH1 CH0
U/B G2 G1 G0 (LSB)
D19 D18 D17 D16
D11 D10 D9 D8
D3 D2 D1 D0 (LSB)
0 1 1 0
0 0 0 0
OF19 OF18 OF17 OF16
OF11 OF10 OF9 OF8
OF3 OF2 OF1 OF0 (LSB)
FS19 FS18 FS17 FS16
FS11 FS10 FS9 FS8
FS3 FS2 FS1 FS0 (LSB)