Timing Characteristics - Analog Devices AD7195 Manual

AD7195

TIMING CHARACTERISTICS

AV = 4.75 V to 5.25 V, DV
DD
otherwise noted.
Table 2.
Parameter
READ AND WRITE OPERATIONS
t
3
t
4
READ OPERATION
t
1
3
t
2
5, 6
t
5
t
6
t
7
WRITE OPERATION
t
8
t
9
t
10
t
11
1 Sample tested during initial release to ensure compliance. All input signals are specified with t
2
See Figure 3 and Figure 4.
3
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V
4
The SCLK active edge is the falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.
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= 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV
DD
Limit at T , T (B Version)
MIN MAX
100
100
0
60
80
0
60
80
10
80
0
10
0
30
25
0
Unit Conditions/Comments
ns min SCLK high pulse width
ns min SCLK low pulse width
ns min CS falling edge to DOUT/RDY active time
ns max DV = 4.75 V to 5.25 V
DD
ns max DV = 2.7 V to 3.6 V
DD
ns min SCLK active edge to data valid delay
ns max DV = 4.75 V to 5.25 V
DD
ns max DV = 2.7 V to 3.6 V
DD
ns min Bus relinquish time after CS inactive edge
ns max
ns min SCLK inactive edge to CS inactive edge
ns min SCLK inactive edge to DOUT/RDY high
ns min CS falling edge to SCLK active edge setup time
ns min Data valid to SCLK edge setup time
ns min Data valid to SCLK edge hold time
ns min CS rising edge to SCLK edge hold time
= t = 5 ns (10% to 90% of DV
R F
Rev. 0 | Page 6 of 44
, unless
DD
1, 2
4
4
) and timed from a voltage level of 1.6 V.
DD
or V limits.
OL OH