Reference Design; Description; Clock; Reset - ST STM32F10 Series Application Note

7

Reference design

7.1

Description

The reference design shown in
integrated microcontroller running at 72 MHz, that combines the new Cortex
RISC CPU core with 512 Kbytes of embedded flash memory and up to 64 Kbytes of high-
speed SRAM
This reference design can be tailored to any other STM32F10xxx device with different
package, using the pins correspondence given in
7.1.1

Clock

Two clock sources are used for the microcontroller:
•
LSE: X1– 32.768 kHz crystal for the embedded RTC
•
HSE: X2– 8 MHz crystal for the STM32F10xxx microcontroller
Refer to
7.1.2

Reset

The reset signal in
• Reset button (B1)
•
Debugging tools via the connector CN1
Refer to
7.1.3

Boot mode

The boot option is configured by setting switches SW2 (Boot 0) and SW1 (Boot 1). Refer to
Section 4.
Note: In low-power mode (more specially in Standby mode) the boot mode is mandatory to be
able to connect to tools (boot the device from the SRAM).
7.1.4

SWJ interface

The reference design shows the connection between the STM32F10xxx and a standard
JTAG connector. Refer to
Note: It is recommended to connect the reset pins so as to be able to reset the application from
the tools.
7.1.5

Power supply

Refer to
.
Section 3.
Figure 14 is active low. The reset sources include:
Section 2.3.
Section
Section 2.
Figure 14, is based on the STM32F103ZE(T6), a highly
Table
5.
AN2586 Rev 8
Reference design
™
7.
-M3 32-bit
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