Reference Design; Description Of Reference Design; Figure 13. Stm32C0 Series Reference Schematic - ST STM32C0 Series Getting Started

6

Reference design

6.1

Description of reference design

The reference design shown in the figure below is based on STM32C031, a highly integrated microcontroller
running at 48 MHz, combining the Cortex
and 12 Kbytes of SRAM.
LSE
The values of capacitors used in combination with X1 and X2 must be chosen according to crystal specifications
(the values indicated for C7, C8, C9, and C10 are given only as an example). To keep a stable NRST signal, the
PCB layout must feature C4 as close as possible to pin 10 (PF2_NRST).
Note: On packages where both OSC_IN/OSC_OUT and OSCX_IN/OSCX_OUT are available, if both LSE and HSE
need to be implemented, the HSE_NOT_REMAPPED bit of the FLASH_OPTR register must be set (default
case).
AN5673 - Rev 2
®
-M0+ 32-bit RISC CPU core with 32 Kbytes of embedded flash memory
Figure 13.
10
9
8
7
6
5
4
3
2
1
VDD
36 35 34 33 32 31
PA15
37
PD0
38
PD1
39
PD2
40
PD3
41
PB3
42
MCU
PB4
43
PB5
44
PB6
45
PB7
46
PB8
47
PB9
48
1 2 3 4 5 6
X2 (32 kHz)
C7 C8
10 pF 10 pF
VREF+
STM32C0 series reference schematic
30 29 28 27 26 25
PB12
24
PB11
23
PB10
22
PB2 PB2
21
PB1
20
PB0
19
PA7
18
PA6
17
PA5
16
PA4
15
PA3
14
PA2
13
7 8 9 10 11 12
X1 (8 MHz)
HSE
C9 C10
20 pF 20 pF
VDD
Reference design
RESET
B1
C4 = 100 nF
R1 = 390 Ω
VREF+ VDD
C5 C1
100 nF 100 nF
AN5673
C6
4.7 µF
MS55475V1
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