Clock Selection; Typical Afe5805 Bench Setup; Clock Selection Jumper Configurations - Texas Instruments AFE5805EVM User Manual

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AFE58XX Evaluation Setup Best Practice
(1) Select the lowest phase noise models
(2) An additional Bandpass filter after the signal source is needed. This serves to filter the harmonic distortion of
the signal generator and band-limit the noise. Without using filter; the SNR and SFDR will be that of the
signal geverator, not that of AFE58XX.
(3) For a coherent AFE58XX evaluation, connect the 10M reference on the back of the clock and to the 10M
reference input on the back of the analog input source. For some equipment, one must also use the on-
screen menus to select "ext Reference"
(4) The Logic Analyzer is used when a large amount of data (> 64K samples) is needed.
(5) If ADSDeSER EVM is chosen then the Logic Analyzer is a must, ADSDeSER EVM does not provide the
function to transfer the data back to PC directly.
The channel order of the AFE5805 outputs is not the same as that of the ADS527x outputs.
Consequently, the channel number on the ADSDeSER-50EVM or AFE5805EVM can be misleading.
Table 2 provides channel-to-channel sequence matching between the ADSDeSER-50EVM and the
AFE5805EVM.
Table 2. Channel-to-Channel Matching Between the AFE5805EVM and ADSDeSER-50EVM
AFE5805 FCLK
ADSDESER FCLK
For example, when an analog signal is present on CH1 of the AFE5805EVM, the corresponding 12-bit
digital output can be seen on CH4 of the ADSDeSER-50EVM.
3.3

Clock Selection

The AFE5805 can be clocked through a transformer-based differential clock, single-ended clock, or future
clock input options provided by U4 as
(a) Transformer Default
SLOU222C – March 2008 – Revised March 2015
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Figure 8. Typical AFE5805 Bench Setup
CH4 CH3 CH2
CH1 CH2 CH3
Figure 9 shows.
(b) Single-Ended Clock
Figure 9. Clock Selection Jumper Configurations
Copyright © 2008–2015, Texas Instruments Incorporated
CH1 CH5 CH6
CH4 CH5 CH6
(c) Future CLK Input Option Based on U4
Board Operation
CH7 CH8 LCLK
CH7 CH8 LCLK
AFE5805EVM
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