Data Analysis; Schematics And Layout; Schematics; Pcb Layout - Texas Instruments AFE5805EVM User Manual

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Board Operation
The clock source of the EVM can be the onboard 40-MHz clock, HP8644 low-jitter clock source, or
external clock source. The best performance of this EVM is achieved when the low-jitter clock source
HP8644 is used. P22, P23, and P18 should be removed in order to disable the onboard clock.
When HP8644 or similar clock sources are unavailable, the onboard 40-MHz clock is the desirable source.
The jumpers P22, P23, and P18 should be configured as shown in
AFE5805EVM). In this mode, the transformer-based differential clock is used.
3.4

Data Analysis

Based on the data file acquired by a logic analyzer, the performance of AFE5805 can be evaluated.
Appendix A provides a solution (TI TSW1400EVM) to analyze the data file using the PC. Appendix B
provides a step by step process on how to download the HSDCPro software. Coherent sampling is
recommended, but is not mandatory. Due to the frequency accuracy requirement of coherence sampling,
two HP8644s are required for generating an ADC clock and analog signal. For most users, this may be
infeasible. Data analysis based on windowing is a more suitable approach.
4

Schematics and Layout

This section provides the schematics, the AFE5805EVM board layout, and the bill of materials.
4.1

Schematics

The schematics appear at the end of the document.
4.2

PCB Layout

The AFE5805EVM uses a six-layer printed-circuit board. The following figures show each layer.
12
AFE5805EVM
Copyright © 2008–2015, Texas Instruments Incorporated
Figure 4
(i.e., the default setup for
SLOU222C – March 2008 – Revised March 2015
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