Board Configuration; I/O And Power Connectors; Afe5805Evm I/O Connectors And Locations - Texas Instruments AFE5805EVM User Manual

Board Configuration

2 Board Configuration
This section describes in detail the locations and functionalities of inputs, outputs, jumpers, and test points
of the AFE5805EVM.
2.1

I/O and Power Connectors

Pin A1 of the AFE5805 is marked by a white dot on its package as well as a white dot on the board. The
positions and functions of the AFE5805EVM connectors are discussed in this section.
Vctrl In
Low Jitter
CLK In
Ext
CLK In
• Analog Inputs Ch1-Ch8 (J1-J3, J5-J7, J9, J10): Single-ended analog signal inputs with 50-Ω
termination and AC-coupling
• CW Output (J4): CW output after I/V translator
• Vcntl Input (J8 optional): VCA gain control voltage of AFE5805, 0 V to 1.2 V, when this SMA connector
is used, shunt P3 must be removed. .
• Low-Jitter CLK Source Input (J11): This input accepts clocks with low-jitter noise, such as HP8644
output. 20- to 50-MHz, 50% duty-cycle clock with 1- to 2-Vrms amplitude can be used. When J11 is
used, ensure that shunts P18, P23, and P22 are removed.
• External CLK Input (J13): ADC Clock input, such as FPGA outputs. However, the AFE5805 does not
achieve satisfactory performances due to the high-jitter noise of the clock.
• ±5-V PWR connector (P2): Power supply input
• Regulated power supply outputs (P1, P4, and P24): 3.3-VA, 3.3-VD, 2.5-VA, 1.8-VD outputs.
Connectors need to be installed.
• RS-232 Input (P17): PC serial port interface for setting AFE5805
• USB input (P25): USB interface to control the AFE5805 (default)
• LVDS Outputs Ch1-Ch8 (P26): Differential LVDS data outputs
• R12 is used to adjust the onboard Vcntl from 0 V to 1.2 V. P3 must be shorted when onboard Vcntl is
used.
4
AFE5805EVM
R12
Figure 2. AFE5805EVM I/O Connectors and Locations
Copyright © 2008–2015, Texas Instruments Incorporated
CW Out
LVDS
Outputs
SLOU222C – March 2008 – Revised March 2015
www.ti.com
USB
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