I/O Memory Of Lcd Driver - Epson S1C6P366 Technical Manual

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.7.6 I/O memory of LCD driver

Table 4.7.6.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.7.6.1 shows the
display memory map.
Register
Address
D3 D2
LDUTY1 LDUTY0 VCCHG LPWR
FF60H
R/W
0 ALOFF ALON
FF61H
R
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
Low
Base address
F000
F010
LPWR: LCD power control (ON/OFF) register (FF60H•D0)
Turns the LCD system voltage circuit ON and OFF.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
When "1" is written to the LPWR register, the LCD system voltage circuit goes ON and generates the LCD
drive voltage. When "0" is written, all the LCD drive voltages go to V
It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage
circuit by writing "1" to the LPWR register.
This control does not affect to SEG terminals that have been set for DC output.
At initial reset, this register is set to "0".
LDUTY0, LDUTY1: LCD drive duty switching register (FF60H•D2, D3)
Selects the LCD drive duty.
LDUTY1 LDUTY0
∗
1
0 1
0 0
At initial reset, this register is set to "0".
52
Table 4.7.6.1 Control bits of LCD driver
∗1
D1 D0 Name Init
LDUTY1 0
LDUTY0 0
VCCHG 0
LPWR 0
∗3 ∗2
0 –
STCD
ALOFF 1
ALON 0
R/W
STCD 0
0 1 2 3 4
Display memory (32 words × 4 bits) R/W
Fig. 4.7.6.1 Display memory map
Table 4.7.6.2 Drive duty setting
Drive duty Common terminal used
1/2 COM0, COM1
1/3 COM0–COM2
1/4 COM0–COM3
1 0
LCD drive duty
switch
General-purpose register (reserved register)
On Off LCD power On/Off
Unused
All Off Normal LCD all OFF control
All On Normal LCD all ON control
Static Dynamic
Common output signal control
5 6 7 8
SS
Maximum segment number
64 (32 × 2)
96 (32 × 3)
128 (32 × 4)
EPSON
Comment
[LDUTY1, 0] 0
Duty 1/4
9 A B C D
level.
Frame frequency ∗
32 Hz
42.7 Hz
32 Hz
∗ When f
= 32.768 kHz
OSC1
S1C6P366 TECHNICAL MANUAL
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