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(3) Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done
before setting data to SD0–SD7.
(4) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source of the programmable timer or in the slave mode.
A/D converter
(1) The A/D converter can operate by inputting the clock from the clock selector. Therefore, it is neces-
sary to select the clock source and to turn the clock output on before starting A/D conversion. Fur-
thermore, it is also necessary that the OSC3 oscillation circuit is operating when using the OSC3 clock.
(2) When using the OSC3 clock as the A/D conversion clock, do not stop the OSC3 oscillation circuit
during A/D conversion. If the OSC3 oscillation circuit stops, correct A/D conversion result cannot be
obtained.
(3) The input clock and analog input terminals should be set when the A/D converter stops. Changing
these settings in the A/D converter operation may cause errors.
(4) To prevent malfunction, do not start A/D conversion (writing "1" to the ADRUN register) when the
A/D conversion clock is not being output from the clock selector, and do not turn the clock off during
A/D conversion.
(5) If the CHS register selects an input channel which is not included in the analog input terminals set by
the PAD register (the PAD register can select several terminals simultaneously), the A/D conversion
does not result in a correct converted value.
(6) During A/D conversion, do not operate the P4n terminals which are not used for analog inputs of the
A/D converter (for input/output of digital signals). It affects the A/D conversion precision.
(7) In the S1C6P366, the value set in the VADSEL register does not affect the operating mode (operating
voltage) of the A/D converter. However, when using the S1C6P366 as a development tool for the
S1C63358/63158, control the operating voltage using the VADSEL register according to the control
sequence of the model (refer to the "Technical Manual").
Buzzer output circuit
Since it generates a buzzer signal that is out of synchronization with the BZON register, hazards may
at times be produced when the signal goes ON/OFF due to the setting of the BZON register.
SVD circuit
(1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the
SVD detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain for 100 µsec minimum
3. Set SVDON to "0"
4. Read SVDDT
(2) The SVD circuit should normally be turned OFF because SVD operation increase current consump-
tion.
(3) Be aware that the SVD circuit in the S1C6P366 does not operate properly if the SVDS register is set to 13
or less, the SVD operation cannot be guaranteed since the lower limit of the operating voltage is 2.7 V.
Interrupt
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
S1C6P366 TECHNICAL MANUAL
EPSON
CHAPTER 7: SUMMARY OF NOTES
121
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