I/O Memory Of Lcd Driver - Epson S1C63656 Technical Manual

4.7.7 I/O memory of LCD driver

Table 4.7.7.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.7.7.1 shows the
display memory map.
Register
Address
D3 D2
LDUTY1 LDUTY0 STCD
FF60H
R/W
0 ALOFF ALON
FF61H
R R/W
LC3 LC2
FF62H
R/W
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
Address
Base
F000H
F010H
F020H
LPWR: LCD power control (on/off) register (FF60H•D0)
Turns the LCD system voltage circuit on and off.
When "1" is written: On
When "0" is written: Off
Reading: Valid
When "1" is written to the LPWR register, the LCD system voltage circuit goes on and generates the LCD
drive voltage. When "0" is written, all the LCD drive voltages go to V
It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage
circuit by writing "1" to the LPWR register.
This control does not affect to SEG terminals that have been set for DC output.
At initial reset, this register is set to "0".
LDUTY0, LDUTY1: LCD drive duty switching register (FF60H•D2, D3)
Selects the LCD drive duty.
LDUTY1
1
1
0
0
At initial reset, this register is set to "0".
S1C63656 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Table 4.7.7.1 Control bits of LCD driver
∗1
D1 D0 Name Init
LDUTY1 0
LPWR
LDUTY0 0
STCD 0
LPWR 0
∗3 ∗2
0 –
0
ALOFF 1
ALON 0
R
∗3 ∗2
0 –
LC3 0
LC1 LC0
LC2 0
LC1 0
LC0 0
Low
0 1 2 3
Display memory (48 words × 4 bits)
Fig. 4.7.7.1 Display memory map
Table 4.7.7.2 Drive duty setting
LDUTY0 Drive duty Common terminal used
1 1/3
0 –
1 –
0 1/4
1 0
LCD drive duty
switch
LCD drive switch
Static Dynamic
LCD power On/Off
On Off
Unused
All Off Normal
LCD all Off control
All On Normal LCD all On control
Unused
LCD contrast adjustment
[LC3–0]
Contrast
4 5 6 7 8 9
R/W
Maximum segment number
COM0–COM2
–
–
COM0–COM3
EPSON
Comment
[LDUTY1, 0] 0
Duty 1/4
0 – 15
Light – Dark
A B C D E F
level.
SS
114 (38 × 3)
–
–
152 (38 × 4)
1,2 3
– 1/3
55