I/O Memory Of A/D Converter - Epson S1C6P366 Technical Manual

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

4.11.6 I/O memory of A/D converter

Table 4.11.6.1 shows the I/O addresses and the control bits for the A/D converter.
Register
Address
D3 D2
VADSEL VDSEL
FF01H
R/W
ADRUN ADCLK CHS1
FFD0H
W
PAD3 PAD2 PAD1
FFD1H
R/W
ADDR3 ADDR2 ADDR1 ADDR0
FFD2H
R
ADDR7 ADDR6 ADDR5 ADDR4
FFD3H
R
0 0
FFE7H
R
0 0
FFF7H
R
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
PAD0–PAD3: A/D converter input control register (FFD1H)
Sets the P40–P43 terminals as the analog input terminals for the A/D converter.
When "1" is written: A/D converter input
When "0" is written: I/O port
Reading: Valid
When "1" is written to PADn, the P4n terminal is set to the analog input terminal ADn. (n = 0–3)
When "0" is written, the terminal is used with the I/O port.
At initial reset, this register is set to "0" (I/O port).
ADCLK: A/D converter clock source selection register (FFD0H•D2)
Selects the clock source for the A/D converter.
When "1" is written: OSC3
When "0" is written: OSC1
Reading: Valid
When "1" is written to ADCLK, OSC3 is selected as the clock source for the A/D converter.
When "0" is written, OSC1 is selected.
At initial reset, this register is set to "0" (OSC1).
86
Table 4.11.6.1 Control bits of A/D converter
∗1
D1 D0 Name Init
VADSEL 0
0 DBON
VDSEL 0
∗3 ∗2
0 –
R R/W
DBON 0
ADRUN 0
CHS0
ADCLK 0
CHS1 0
R/W
CHS0 0
PAD3 0
PAD0
PAD2 0
PAD1 0
PAD0 0
∗2
ADDR3 –
∗2
ADDR2 –
∗2
ADDR1 –
∗2
ADDR0 –
∗2
ADDR7 –
∗2
ADDR6 –
∗2
ADDR5 –
∗2
ADDR4 –
∗3 ∗2
0 –
0 EIAD
∗3 ∗2
0 –
∗3 ∗2
0 –
R/W
EIAD 0
∗3 ∗2
0 –
0 IAD
∗3 ∗2
0 –
∗3 ∗2
0 –
R/W
IAD 0
1 0
(V ) (V ) (Power source selection for A/D converter)
C2 DD
(V ) (V ) (Power source selection for oscillation system voltage regulator)
C2 DD
Unused
(On) (Off) (Voltage doubler On/Off)
Start Invalid
A/D Run/Off control
OSC3 OSC1 A/D input clock selection
A/D input
channel
selection
Enable Disable P43 input channel enable/disable control
Enable Disable
P42 input channel enable/disable control
Enable Disable P41 input channel enable/disable control
Enable Disable P40 input channel enable/disable control
A/D converted data (D0–D3)
A/D converted data (D4–D7)
Unused
Unused
Unused
Enable Mask Interrupt mask register (A/D converter)
(R) (R) Unused
Yes No Unused
(W) (W)
Unused
Reset Invalid Interrupt factor flag (A/D converter)
EPSON
Comment
[CHS1, 0] 0 1 2
Input channel
P40 P41 P42
S1C6P366 TECHNICAL MANUAL
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P43