Bios Organization And System Memory Map; Post Checkpoint Codes; Post 80 Codes - RadiSys PROCELERANT CE915GMA Product Manual

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BIOS organization and system memory map

POST checkpoint codes

POST 80 codes

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Range
0 to 640 KB 0000 0000
640 KB to 1 MB 000A 0000
000C 0000
000D 0000
000E 0000
1 MB to 512 MB 0010 0000
512 MB to Top 1000 0000
1 MB
Top 1 MB FFF0 0000
1. If no BIOS extensions and ISA bus (aliased), not cacheable.
2. If no DRAM and ISA bus (aliased), not cacheable.
his section lists the POST checkpoint codes that the system BIOS may send to I/O port 80h
during POST. They are presented in an alphabetically ascending order and are not
necessarily in order of execution.
If an error occurs at any of the listed checkpoints, the system attempts to generate beeps
to indicate where the error occurred. To hear the beeps, connect a speaker (not included)
to the speaker pin on the front panel I/O header. Beep codes are derived from the
checkpoint code in the following way:
1. The 8-bit hexadecimal checkpoint code is converted to binary, then the binary number
is divided into four 2-bit groups. For example:
Checkpoint code 20h = 00100000 = 00-10-00-00
2. Each 2-bit group is converted to a one-based number, and 1 is added to indicate the
number of beeps:
3. 00 10 00 00 = 1-3-1-1 beeps
Note: Only standard Phoenix TrustedCore BIOS POST 80 codes are listed in the tables
below. If you encounter other POST 80 codes, contact RadiSys for further assistance.
Description
0009 FFFF DOS compatibility area
000B FFFF Legacy video DRAM, mapped to the video
module (SMM memory) 128 K
000C BFFF Write-protected DRAM containing
shadowed video BIOS (48 KB)
000D FFFF BIOS extensions
000F FFFF System BIOS shadow
0FFF FFFF DRAM (511 MB)
FFEF FFFF ISA bus (aliased)
FFFF FFFF System ROM (1MB flash boot device)
System Resources
Cacheable
Yes
No
Yes
Yes 1
Yes
Yes
2
No
No